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PDF CAT24AA02 Data sheet ( Hoja de datos )
| Número de pieza | CAT24AA02 | |
| Descripción | 1-Kb and 2-Kb I2C CMOS Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT24AA02 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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CAT24AA01, CAT24AA02
1-Kb and 2-Kb I2C CMOS Serial EEPROM
FEATURES
Supports Standard and Fast I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA)
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant TSOT-23 5-lead and SOIC
8-lead packages
DESCRIPTION
The CAT24AA01/24AA02 are 1-Kb and 2-Kb CMOS
Serial EEPROM devices internally organized as
128x8/256x8 bits.
They feature a 16-byte page write buffer and support
both the Standard (100kHz) and the Fast (400kHz)
I2C protocols.
In contrast to the CAT24C01/24C02, the
CAT24AA01/24AA02 have no external address
pins, and are therefore suitable in applications
that require a single CAT24AA01/02 on the I2C
bus.
For Ordering Information details, see page 12.
PIN CONFIGURATION
SOIC (W)
NC 1
NC 2
8 VCC
7 WP
NC 3
6 SCL
VSS 4
5 SDA
TSOT-23 (TD)
SCL 1
5 WP
VSS 2
SDA 3
4 VCC
* For the location of Pin 1, please consult the corresponding
package drawing.
PIN FUNCTIONS
Pin Name
SDA
SCL
WP
VCC
VSS
Function
Serial Data/Address
Clock Input
Write Protect
Power Supply
Ground
FUNCTIONAL SYMBOL
VCC
SCL
CAT24AA01
CAT24AA02
WP
VSS
SDA
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1120 Rev. B
1 page  
Figure 1: Start/Stop Timing
SCL
SDA
START
CONDITION
CAT24AA0w1w, wC.DAataTSh2ee4t4AU.Acom02
STOP
CONDITION
Figure 2: Slave Address Bits
1 0 1 0 0 0 0 R/¯W¯
Figure 3: Acknowledge Timing
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
18
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
BUS RELEASE DELAY (RECEIVER)
9
ACK SETUP (≥ tSU:DAT)
Figure 4: Bus Timing
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
tSU:STO
tBUF
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1120 Rev. B
5 Page 
TSOT 5-Lead (TD)(1)(2)
D
e
E1 E
TOP VIEW
CAT24AA0w1w, wC.DAataTSh2ee4t4AU.Acom02
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
L1
L2
θ
MIN
0.01
0.80
0.30
0.12
0.30
0º
NOM
0.05
0.87
0.15
2.90 BSC
2.80 BSC
1.60 BSC
0.95 TYP
0.40
0.60 REF
0.25 BSC
MAX
1.00
0.10
0.90
0.45
0.20
0.50
8º
A2 A
b
SIDE VIEW
A1
θ
L
L1
END VIEW
c L2
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-193.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-1120 Rev. B
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CAT24AA02.PDF ] | |
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