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Teilenummer | ADP4100 |
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Beschreibung | Programmable Multi-Phase Synchronous Buck Converter | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 22 Seiten ADP4100
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Programmable Multi-Phase
Synchronous Buck
Converter
The ADP4100 is an integrated power control IC for VR11.1
applications. The ADP4100 can be programmed for 1−, 2−, 3−, 4−, 5−
or 6−phase operation, allowing for the construction of up to six
complementary buck switching stages. The ADP4100 supports PSI,
which is a power state indicator and can be used to reduce number of
operating phases at light loads.
The ADP4100 is optimized for converting a 12 V main supply into
the core supply voltage required by high performance Intel processors.
It uses an internal 8−bit DAC to read the voltage identification (VID)
code directly from the processor, which is used to set the output
voltage between 0.375 V and 1.6 V.
Features
• Supports Both VR11 and VR11.1 Specifications
• Digitally Programmable 0.375 V to 1.6 V Output
• Selectable 1−, 2−, 3−, 4−, 5− or 6−Phase Operation
• Fast−Enhanced PWM FlexModet
• TRDET to Improve Load Release
• Active Current Balancing Between All Output Phases
• Supports On−The−Fly (OTF) VID Code Changes
• Supports PSI − Power Saving Mode
• Short Circuit Protection with Latchoff Delay
• This is a Pb−Free Device
Typical Applications
• Servers
• Desktop PC’s
• POLs (Memory)
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LFCSP48
CASE 932AD
MARKING
DIAGRAM
ADP4100
JCPZ
#YYWW
XXXXX
CCCCC
xx = Device Code
# = Pb−Free Package
YYWW = Date Code
XXX = Assembly Lot
CCC = Country of Origin
PIN ASSIGNMENT
NC 1
NC 2
NC 3
NC 4
EN 5
GND 6
PSI_SET 7
LLSET 8
IMON 9
TTSENSE 10
VRHOT 11
IREF 12
PIN 1
INDICATOR
ADP4100
TOP VIEW
(Not to Scale)
36 PWM1
35 PWM2
34 PWM3
33 PWM4
32 PWM5
31 PWM6
30 SW1
29 SW2
28 SW3
27 SW4
26 SW5
25 SW6
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2008
March, 2008 − Rev. P0
1
ORDERING INFORMATION
Device*
Package
Shipping†
ADP4100JCPZ−REEL LFCSP48 2500/Tape & Reel
ADP4100JCPZ−RL7 LFCSP48 750/Tape & Reel
*The “Z’ suffix indicates Pb−Free package.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
ADP4100/D
ADP4100
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ELECTRICAL CHARACTERISTICS
Vin = (5.0 V) FBRTN − GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted.
Parameter
Test Conditions
Symbol
Min Typ Max Unit
Reference Current
Reference Bias Voltage
Reference Bias Current
RIREF = 121 kW
VIREF
IIREF
1.75 1.8 1.85
V
15 mA
Error Amplifier
Output Voltage Range (Note 6)
Accuracy
Load Line Positioning Accuracy
Relative to nominal DAC output, referenced to
FBRTN (see Figure 4)
In startup
VCOMP
VFB
0
7
4.4 V
7 mV
VFB(BOOT) 1.093 1.1 1.107 V
−77 −80 −83 mV
LLSET Input Voltage Range
−250
250 mV
LLSET Input Bias Current
−10 10 nA
Differential Non−linearity
−1.0 +1.0 LSB
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
RIREF = 121 kW
FB forced to VOUT −3%
COMP = FB
COMP = FB
IFB 14.2 16 17.7 mA
IFBRTN
100 200 mA
ICOMP
500 mA
GBW(ERR)
20 MHz
25 V/ms
BOOT Voltage Hold Time
VID Inputs
Input Low Voltage
Input High Voltage
Input Current
VID Transition Delay Time (Note 6)
Internal Timer
VID(X)
VID(X)
VID code change to FB change
tBOOT
VIL(VID)
VIH(VID)
IIN(VID)
2.0 ms
0.3
0.8
−5.0
200
V
V
mA
ns
No CPU Detection Turn−Off Delay VID code change to PWM going low
Time (Note 6)
5.0 ms
Oscillator
Frequency Range (Note 6)
Frequency Variation
Output Voltage
TA = 25°C, RT = 270 kW, 6−phase
TA = 25°C, RT = 130 kW, 6−phase
TA = 25°C, RT = 68 kW, 6−phase
RT = 500 kW to GND
RAMPADJ Output Voltage
RAMPADJ Input Current Range
RAMPADJ − FB, VFB = 1V, IRAMPADJ = −60 mA
Current Sense Amplifier
Offset Voltage
CSSUM − CSREF (see Figure 5)
Input Bias Current, CSREF
CSREF = 1.0 V
Input Bias Current, CSSUM
CSREF = 1.0 V
Gain Bandwidth Product
CSSUM = CSCOMP
Slew Rate
Input Common−Mode Range
CCSCOMP = 10pF
CSSUM and CSREF
Output Voltage Range
Output Current
Current−Limit Latchoff Delay time Internal Timer
6. Guaranteed by design or bench characterization, not tested in production.
fOSC
fPHASE
VRT
VRAMPADJ
IRAMPADJ
VOS(CSA)
IBIAS(CSREF)
IBIAS(CSSUM)
GBW(CSA)
ICSCOMP
0.25
225
1.93
−50
5.0
−1.0
−20
−10
0
0.05
245
500
850
2.03
10
10
500
8.0
9.0 MHz
265 kHz
2.13 V
+50 mV
60 mA
+1.0
+20
+10
3.0
3.0
mV
mA
nA
MHz
V/ms
V
V
mA
ms
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6
6 Page ADP4100
through a resistor, RB, to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN is
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 100 mA to allow
accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
Output Current Sensing
The ADP4100 provides a dedicated Current−Sense
Amplifier (CSA) to monitor the total output current for
proper voltage positioning vs. load current, for the IMON
output and for current−limit detection. Sensing the load
current at the output gives the total real time current being
delivered to the load, which is an inherently more accurate
method than peak current detection or sampling the current
across a sense element such as the low−side MOSFET. This
amplifier can be configured several ways, depending on the
objectives of the system, as follows:
• Output inductor DCR sensing without a thermistor for
lowest cost.
• Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor
temperature.
• Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF
pin, which is connected to the average output voltage. The
inputs to the amplifier are summed together through
resistors from the sensing element, such as the switch node
side of the output inductors, to the inverting input CSSUM.
The feedback resistor between CSCOMP and CSSUM sets
the gain of the amplifier and a filter capacitor is placed in
parallel with this resistor. The gain of the amplifier is
programmable by adjusting the feedback resistor. This
difference signal is used internally to offset the VID DAC
for voltage positioning.
The difference between CSREF and CSCOMP is used as
a differential input for the current−limit comparator.
To provide the best accuracy for sensing current, the CSA
is designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors to make it
extremely accurate.
Current−Limit Setpoint
The current limit threshold on the ADP4100 is
programmed by a resistor between the ILIMFS pin and the
CSCOMP pin. The ILIMFS current, IILIMFS, is compared
with an internal current reference of 22 mA. If IILIMFS
exceeds 22 mA then the output current has exceeded the limit
and the current limit protection is tripped.
IILIMFS
+
VILIMFS * VCSCOMP
RILIMFS
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(eq. 2)
Where: VILIMFS = VCSREF
IILIMFS
+
VCSREF * VCSCOMP
RILIMFS
(eq. 3)
VCSREF
*
VCSCOMP
+
RCS
RPH
RL
ILOAD
Where: RL = DCR of the Inductor
Assuming that:
RCS
RPH
RL + 1 mW
(eq. 4)
i.e. the external circuit is set up for a 1 mW Loadline then the
RILIMFS is calculated as follows:
IILIMFS
+
1
mW ILOAD
RLIMITS
(eq. 5)
Assuming we want a current limit of 150 A that means that
ILIMFS must equal 22 mA at that load.
22
mA
+
1
mW 150
RLIMITFS
A
(eq. 6)
Solving this equation for RLIMITFS we get 6.8 kW. Closest
1% resistor is 6.81 kW.
Current−Limit, Short−Circuit and Latchoff Protection
If the current limit is reached and TD5 has completed, an
internal latchoff delay time will start, and the controller will
shut down if the fault is not removed. This delay is four times
longer than the delay time during the startup sequence. The
current limit delay time only starts after the TD5 has
completed. If there is a current limit during startup, the
ADP4100 will go through TD1 to TD5, and then start the
latchoff time. Because the controller continues to cycle the
phases during the latchoff delay time, if the short is removed
before the timer is complete, the controller can return to
normal operation.
The latchoff function can be reset by either removing and
reapplying the supply voltage to the ADP4100, or by
toggling the EN pin low for a short time.
During startup when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit limits the internal COMP
voltage to the PWM comparators to 1.5 V. This limits the
voltage drop across the low−side MOSFETs through the
current balance circuitry. Typical overcurrent latchoff
waveforms are shown in Figure 9).
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12
12 Page | ||
Seiten | Gesamt 22 Seiten | |
PDF Download | [ ADP4100 Schematic.PDF ] |
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