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PDF ADP3290 Data sheet ( Hoja de datos )
| Número de pieza | ADP3290 | |
| Descripción | Programmable 2- to 4-Phase Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ADP3290
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8-Bit, Programmable
2- to 4-Phase Synchronous
Buck Controller
The ADP3290 is a highly efficient, multi−phase, synchronous buck
switching regulator controller optimized for converting a 12 V main
supply voltage into the core supply voltage of high performance Intel
processors. It uses an internal 8−bit DAC to read a Voltage
Identification (VID) code directly from the processor, to set the output
voltage between 0.5 V and 1.6 V.
This device uses a multi−mode control architecture to drive the
logic−level PWM outputs. The switching frequency can be
programmed according to VR size and efficiency. The chip can
provide 2−, 3− or 4−phase operation, allowing for the construction of
up to four complementary buck switching stages.
The ADP3290 also includes programmable no load offset and load
line slope setting function that adjusts the output voltage as a function
of the load current, optimally positioning it for a system transient. The
ADP3290 also provides accurate and reliable short−circuit protection,
adjustable current limit, and a delayed power−good output that
accommodates On−The−Fly (OTF) output voltage changes requested
by the CPU.
Features
• Selectable 2−, 3−, or 4−Phase Operation at Up to 1 MHz Per Phase
• ±7 mV Worse−Case Differential Sensing Error
• Logic−Level PWM Outputs for Interface to External High Power
Drivers
• Fast−Enhanced PWM FlexModet for Excellent Load Transient
Performance
• TRDET to Improve Load Release
• Active Current Balancing Between All Output Phases
• Built−In Power−Good/Crowbar Blanking Supports Dynamic
VID Code Changes
• Digitally Programmable 0.5 V to 1.6 V Output Supports
VR11.1 Specification
• Programmable Overcurrent Protection with Programmable
Latchoff Delay
• This is a Pb−Free Device
Typical Applications
• Desktop PC Power Supplies for:
♦ Next Generation Intel® Processors
♦ VRM Modules
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Package Name
LFCSP40
CASE Number
932AC
MARKING
DIAGRAM
ADP3290
#_YYYYYY
ZZZZZZZZ
CCCCC
ADP3290 = Device Code
# = Pb−Free Package
YY = Date Code
ZZ = Assembly Lot Number
CC = Country of Origin
PIN ASSIGNMENT
EN 1
PWRGD 2
FBRTN 3
FB 4
COMP 5
SS 6
DELAY 7
TRDET 8
VRHOT 9
TTSNS 10
PIN 1
INDICATOR
ADP3290
TOP VIEW
30 PWM1
29 PWM2
28 PWM3
27 PWM4
26 ODN
25 SW1
24 SW2
23 SW3
22 SW4
21 IMON
ORDERING INFORMATION
Device
Package
Shipping†
ADP3290JCPZ−RL LFCSP40 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
July, 2009 − Rev. 2
1
Publication Order Number:
ADP3290/D
1 page  
ADP3290
PIN ASSIGNMENT
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Pin No. Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 to 25
26
27 to 30
31
32 to 39
40
EN
PWRGD
FBRTN
FB
COMP
SS
DELAY
TRDET
VRHOT
TTSNS
ILIM
RT
RAMP
LLINE
CSREF
CSSUM
CSCOMP
GND
OD
IREF
IMON
SW4 to
SW1
ODN
PWM4 to
PMW1
VCC
VID7 to
VID0
PSI
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Power−Good Output. Open−drain output that signals when the output voltage is outside of the proper operating range.
Feedback Return. VID DAC and error amplifier input for remote sensing of the output voltage.
Feedback Input. Error amplifier reference for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no−load offset point.
Error Amplifier Output and Compensation Point.
Soft−Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft−start
ramp−up time. After startup, pin used to control DVID slew−rate.
Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent
latchoff delay time, boot voltage hold time, EN delay time, and PWRGD delay time.
Transient detection output. This pin is pulled low when a load release transient is detected.
VR Hot Output. Active high open−drain output that signals when the temperature of the temperature sensor
connected to TTSNS exceeds the programmed VRHOT temperature threshold.
VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense
the temperature at the desired thermal monitoring point.
Current Sense and Limit Pin. Connecting a resistor from this pin to CSCOMP sets the internal current sensing
signal for current limit and IMON.
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the PWM
oscillator frequency.
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage to this pin sets the slope
of the internal PWM ramp.
Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to
the center point of a resistor divider between CSCOMP and CSREF. Connecting LLINE to CSREF disables
positioning.
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power−good and crowbar functions. This pin should be connected to the common point of the
output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents
together to measure the total output current.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the
current sense amplifier and the positioning loop response time.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Output Disable Logic Output for phase 1. This pin is actively pulled low when the EN input is low or when VCC is
below its UVLO threshold to signal to the Driver IC that the driver high−side and low−side outputs should go low.
Current Reference Input. An external resistor from this pin to ground sets the internal reference current used to
generate IFB, IDELAY, ISS, ICL, and ITTSNS.
IMON Total Current Output Pin. A resistor/capacitor from this pin to FBRTN/VSS Sense sets the IMON signal.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
Output Disable Logic output for PSI Operation. This pin is pulled low when PSI is low, otherwise it functions the
same as OD.
Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3121. Connecting the PWM4, and/or PWM3 output to VCC causes that phase to turn off, allowing the
ADP3290 to operate as a 2−, 3−, or 4−phase controller.
Supply Voltage for the Device. A 340W resistor should be placed between the 12 V system supply and the VCC
pin. The internal shunt regulator maintains VCC = 5.0 V.
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a Logic 0 if left open.
When in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V.
Power State Indicator Input. Pulling this pin low places controller in lower power state operation.
NOTE: True no connect. Printed circuit board traces are allowable.
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5
5 Page 
ADP3290
Voltage Control Mode
A high gain, bandwidth voltage mode error amplifier is
used for the voltage mode control loop. The control input
voltage to the positive input is set via the VID logic
according to the voltages listed.
This voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location
with Resistor RB and is used for sensing and controlling the
output voltage at this point. A current source from the FB pin
flowing through RB is used for setting the no load offset
voltage from the VID voltage. The no load voltage is
negative with respect to the VID DAC. The main loop
compensation is incorporated into the feedback network
between FB and COMP.
Fast Enhanced Transient Modes
The ADP3290 incorporates enhanced transient response
for both load steps and load release. For load steps, it senses
the error amp to determine if a load step has occurred and
sequences the proper number of phases on to ramp up the
output current.
For load release, it also senses the error amp and uses the
load release information to trigger the TRDET pin, which is
then used to adjust the feedback for optimal positioning
especially during high frequency load steps.
Additional information is used during load transients to
ensure proper sequencing and balancing of phases during
high frequency load steps as well as minimizing stress on the
components such as the input filter and MOSFETs.
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GND, and the capacitor is charged up to the 1.1 V boot
voltage by the SS amplifier, which has a limited output
current of 15 mA. The voltage at the FB pin follows the
ramping voltage on the SS pin, limiting the inrush current
during startup. The soft−start time depends on the value of
the boot voltage and CSS.
Once the SS voltage is within 100 mV of the boot voltage,
the boot voltage delay time (TD3 in Figure 5) is started. The
end of the boot voltage delay time signals the beginning of the
second soft−start time (TD4 in Figure 5). The SS voltage now
changes from the boot voltage to the programmed VID DAC
voltage (either higher or lower) using the SS amplifier with
the limited 15 mA output current. The voltage of the FB pin
follows the ramping voltage of the SS pin, limiting the inrush
current during the transition from the boot voltage to the final
DAC voltage. The second soft−start time depends on the boot
voltage, the programmed VID DAC voltage, and CSS.
Once TD5 has finished, the SS pin is then used to limit the
slew−rate of DVID steps. The current source is changed to
75 mA and the DVID slew−rate becomes 5 X the soft−start
slew−rate. Typically, the SS slew−rate is 2 mV/mS, so the
DVID becomes 10 mV/mS.
If EN is taken low or if VCC drops below UVLO, DELAY
and SS are reset to ground to be ready for another soft−start
cycle. Figure 6 shows typical startup waveforms for the
ADP3290.
Delay Timer
The delay times for the startup timing sequence are set
with a capacitor from the DELAY pin to ground. In UVLO,
or when EN is logic low, the DELAY pin is held at ground.
After the UVLO and EN signals are asserted, the first delay
time (TD1 in Figure 5) is initiated. A 15 mA current flows out
of the DELAY pin to charge CDLY. A comparator monitors
the DELAY voltage with a threshold of 1.7 V. The delay time
is therefore set by the 15 mA charging a capacitor from 0 V
to 1.7 V. This DELAY pin is used for multiple delay timings
(TD1, TD3, and TD5) during the startup sequence. Also,
DELAY is used for timing the current limit latchoff, as
explained in the Current Limit, Short−Circuit, and Latchoff
Protection section.
Soft−Start
The soft−start times for the output voltage are set with a
capacitor from the SS pin to ground. After TD1 and the
phase detection cycle have been completed, the SS time
(TD2 in Figure 5) starts. The SS pin is disconnected from
Figure 6. Typical Startup Waveform
1-Vo, 2-EN, 3-SS, 4-DELAY, D0−D3-PWM1~4
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11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3290.PDF ] | |
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