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Número de pieza | PDTA115T | |
Descripción | PNP resistor-equipped transistors | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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PDTA115T series
PNP resistor-equipped transistors; R1 = 100 kΩ, R2 = open
Rev. 05 — 2 September 2009
Product data sheet
1. Product profile
1.1 General description
PNP resistor-equipped transistors.
Table 1. Product overview
Type number
Package
NXP
PDTA115TE
SOT416
PDTA115TK
SOT346
PDTA115TM
SOT883
PDTA115TS[1]
SOT54 (TO-92)
PDTA115TT
SOT23
PDTA115TU
SOT323
JEITA
SC-75
SC-59
SC-101
SC-43A
-
SC-70
[1] Also available in SOT54A and SOT54 variant packages (see Section 2)
NPN complement
PDTC115TE
PDTC115TK
PDTC115TM
PDTC115TS
PDTC115TT
PDTC115TU
1.2 Features
I Built-in bias resistors
I Simplifies circuit design
I Reduces component count
I Reduces pick and place costs
1.3 Applications
I General purpose switching and
amplification
I Inverter and interface circuits
I Circuit drivers
1.4 Quick reference data
Table 2.
Symbol
VCEO
IO
R1
Quick reference data
Parameter
collector-emitter voltage
output current (DC)
bias resistor 1 (input)
Conditions
open base
Min Typ Max Unit
- - −50 V
- - −100 mA
70 100 130 kΩ
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PDTA115T series
PNP resistor-equipped transistors; R1 = 100 kΩ, R2 = open
7. Characteristics
Table 8. Characteristics
Tamb = 25 °C unless otherwise specified
Symbol Parameter
Conditions
ICBO
collector-base cut-off VCB = −50 V; IE = 0 A
current
ICEO
IEBO
collector-emitter
cut-off current
emitter-base cut-off
current
VCE = −30 V; IB = 0 A
VCE = −30 V; IB = 0 A;
Tj = 150 °C
VEB = −5 V; IC = 0 A
hFE
VCEsat
DC current gain
collector-emitter
saturation voltage
VCE = −5 V; IC = −1 mA
IC = −5 mA; IB = −0.25 mA
R1 bias resistor 1 (input)
Cc collector capacitance VCB = −10 V; IE = ie = 0 A;
f = 1 MHz
Min Typ Max Unit
-
-
−100
nA
- - −1 µA
- - −50 µA
-
-
−100
nA
100 -
--
-
−150
mV
70 100 130 kΩ
- - 3 pF
103
hFE
102
001aab511
(1)
(2)
(3)
10
−10−1
−1
−10 −102
IC (mA)
VCE = −5 V.
(1) Tamb = 100 °C.
(2) Tamb = 25 °C.
(3) Tamb = −40 °C.
Fig 1. DC current gain as a function of collector
current; typical values
−1 001aab512
VCEsat
(V)
−10−1
(1)
(2)
(3)
−10−2
−10−1
−1
−10 −102
IC (mA)
IC/IB = 20.
(1) Tamb = 100 °C.
(2) Tamb = 25 °C.
(3) Tamb = −40 °C.
Fig 2. Collector-emitter saturation voltage as a
function of collector current; typical values
PDTA115T_SER_5
Product data sheet
Rev. 05 — 2 September 2009
© NXP B.V. 2009. All rights reserved.
5 of 17
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PDTA115T series
PNP resistor-equipped transistors; R1 = 100 kΩ, R2 = open
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
SOT54 variant
E
d
1
2
D
3
b1
L2
AL
L1
c
e1
b
e1
e
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A b b1 c D d
mm
5.2
5.0
0.48 0.66 0.45
0.40 0.55 0.38
4.8
4.4
1.7
1.4
E
e
e1
L
L1(1) L2
max max
4.2
3.6
2.54
1.27
14.5
12.7
2.5
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT54 variant
ISSUE DATE
04-06-28
05-01-10
Fig 8. Package outline SOT54 variant
PDTA115T_SER_5
Product data sheet
Rev. 05 — 2 September 2009
© NXP B.V. 2009. All rights reserved.
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PDF Descargar | [ Datasheet PDTA115T.PDF ] |
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