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PDF PDTA113E Data sheet ( Hoja de datos )
| Número de pieza | PDTA113E | |
| Descripción | PNP resistor-equipped transistors | |
| Fabricantes | NXP Semiconductors | |
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PDTA113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ
Rev. 05 — 2 September 2009
Product data sheet
1. Product profile
1.1 General description
PNP Resistor-Equipped Transistors (RET).
Table 1. Product overview
Type number Package
NXP
PDTA113EE
SOT416
PDTA113EK
SOT346
PDTA113EM
SOT883
PDTA113ES[1] SOT54 (TO-92)
PDTA113ET
SOT23
PDTA113EU
SOT323
JEITA
SC-75
SC-59A
SC-101
SC-43A
-
SC-70
JEDEC
-
TO-236
-
TO-92
TO-236AB
-
[1] Also available in SOT54A and SOT54 variant packages (see Section 2)
NPN
complement
PDTC113EE
PDTC113EK
PDTC113EM
PDTC113ES
PDTC113ET
PDTC113EU
1.2 Features
I Built-in bias resistors
I Simplifies circuit design
I Reduces component count
I Reduces pick and place costs
1.3 Applications
I General purpose switching and
amplification
I Inverter and interface circuits
I Circuit drivers
1.4 Quick reference data
Table 2.
Symbol
VCEO
IO
R1
R2/R1
Quick reference data
Parameter
collector-emitter voltage
output current (DC)
bias resistor 1 (input)
bias resistor ratio
Conditions
open base
Min Typ Max Unit
- - −50 V
- - −100 mA
0.7 1
1.3 kΩ
0.8 1
1.2
1 page  
NXP Semiconductors
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PDTA113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ
7. Characteristics
Table 8. Characteristics
Tamb = 25 °C unless otherwise specified
Symbol Parameter
Conditions
ICBO
collector-base cut-off VCB = −50 V; IE = 0 A
current
ICEO
IEBO
collector-emitter
cut-off current
emitter-base cut-off
current
VCE = −30 V; IB = 0 A
VCE = −30 V; IB = 0 A;
Tj = 150 °C
VEB = −5 V; IC = 0 A
hFE
VCEsat
DC current gain
collector-emitter
saturation voltage
VCE = −5 V; IC = −40 mA
IC = −30 mA; IB = −1.5 mA
VI(off)
VI(on)
off-state input voltage VCE = −5 V; IC = −100 µA
on-state input voltage VCE = −300 mV; IC = −20 mA
R1 bias resistor 1 (input)
R2/R1
bias resistor ratio
Cc collector capacitance VCB = −10 V; IE = ie = 0 A;
f = 1 MHz
Min Typ Max Unit
-
-
−100
nA
- - −1 µA
- - −50 µA
- - −4 mA
30 -
--
-
−150
mV
- −1.3 −0.5 V
−2 −1.7 -
V
0.7 1
1.3 kΩ
0.8 1
1.2
- - 2 pF
PDTA113E_SER_5
Product data sheet
Rev. 05 — 2 September 2009
© NXP B.V. 2009. All rights reserved.
5 of 18
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NXP Semiconductors
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PDTA113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ
Plastic single-ended leaded (through hole) package; 3 leads (wide pitch)
SOT54A
c
E
d
1
D
2
3
b1
AL
L2
L1
b
e1
e
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A
b b1 c
Dd
mm
5.2
5.0
0.48 0.66 0.45
0.40 0.55 0.38
4.8
4.4
1.7
1.4
E
e
e1
L
L1(1)
max.
L2
4.2
3.6
5.08
2.54
14.5
12.7
3
3
2
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT54A
ISSUE DATE
97-05-13
04-06-28
Fig 9. Package outline SOT54A
PDTA113E_SER_5
Product data sheet
Rev. 05 — 2 September 2009
© NXP B.V. 2009. All rights reserved.
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