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PCF85133 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF85133
Beschreibung Universal LCD driver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF85133 Datasheet, Funktion
www.DataSheet4U.com
PCF85133
Universal LCD driver for low multiplex rates
Rev. 1 — 17 February 2009
Product data sheet
1. General description
The PCF85133 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 80 segments and can easily
be cascaded for larger LCD applications. The PCF85133 is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremental addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
2. Features
I Single-chip LCD controller and driver
I Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing
I Selectable display bias configuration: static, 12 or 13
I Selectable frame frequency: 82 Hz or 110 Hz
I Internal LCD bias generation with voltage-follower buffers
I 80 segment drives:
N Up to 40 7-segment numeric characters
N Up to 21 14-segment alphanumeric characters
N Any graphics of up to 320 elements
I 80 × 4 bit RAM for display data storage
I Auto-incremental display data loading across device subaddress boundaries
I Display memory bank switching in static and duplex drive modes
I Versatile blinking modes
I Independent supplies possible for LCD and logic voltages
I Wide power supply range: from 1.8 V to 5.5 V
I Wide LCD supply range for low-threshold LCDs, for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs: from 2.5 V to 6.5 V
I Low power consumption
I 400 kHz I2C-bus interface
I May be cascaded for large LCD applications (up to 5120 elements possible)
I May be cascaded with PCF8532 to gain more flexibility in the number of addressable
segments
I No external components
I Compatible with Chip-On-Glass (COG) technology
I Manufactured using silicon gate CMOS process






PCF85133 Datasheet, Funktion
NXP Semiconductors
www.DataSheet4U.com
PCF85133
Universal LCD driver for low multiplex rates
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
V on(RMS)
=
V LCD
-1n- + (n 1) × 1-----+1-----a-- 2
-----------------------------n-------------------------------
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 3 for 1:3 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation:
V off (RMS) = V LCD -a-n--2---×----(--(-1-2----a+-----+a---)-n--2--)
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation:
-V----o---n---(--R---M----S--)- =
Voff (RMS)
-((--aa-----+-----11---)-)--22----++-----((--nn---------11----))
Using Equation 3, the discrimination for an LCD drive mode of
(3)
1:3 multiplex with 12 bias is 3 = 1.732
1:4 multiplex with 12 bias is ----3-2---1-- = 1.528
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
1:3 multiplex (12 bias):V LCD = 6 × V off (RMS) = 2.449V off (RMS)
1:4 multiplex (12 bias): V LCD = (---4-----×--3-------3----) = 2.309V off (RMS)
These compare with V LCD = 3V off (RMS) when 13 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
PCF85133_1
Product data sheet
Rev. 1 — 17 February 2009
© NXP B.V. 2009. All rights reserved.
6 of 41

6 Page









PCF85133 pdf, datenblatt
NXP Semiconductors
www.DataSheet4U.com
PCF85133
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF85133 are timed by a frequency fclk
which either is derived from the built-in oscillator frequency fosc:
f clk = -f--6-o--4-s--c
(4)
or equals an external clock frequency fclk(ext):
f clk = f clk(ext)
(5)
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output
from pin CLK provides the clock signal for cascaded PCF85133s in the system. After
power-up, pin SDA must be HIGH to guarantee that the clock starts.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state.
7.6 Timing
The clock frequency fclk determines the LCD frame frequency ffr and is calculated as
follows:
f fr = -f-2--c-4--l-k-
(6)
The internal clock frequency fclk can be selected using pin FF. As a result 2 frame
frequencies are available: 82 Hz or 110 Hz (typical), see Table 6.
Table 6. LCD frame frequencies
Pin FF tied to
Typical clock frequency (Hz)
VDD 1970
VSS 2640
LCD frame frequency (Hz)
82
110
The timing of the PCF85133 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between all the PCF85133s in the system.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
PCF85133_1
Product data sheet
Rev. 1 — 17 February 2009
© NXP B.V. 2009. All rights reserved.
12 of 41

12 Page





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