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PDF PN512 Data sheet ( Hoja de datos )
| Número de pieza | PN512 | |
| Descripción | Transmission Module | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PN512
Transmission Module
Rev. 3.4 — 8 September 2009
111334
www.DataSheet4U.com
Product data sheet
PUBLIC
1. Introduction
This Product data sheet document describes the functionality of the transceiver IC
PN512. It includes functional and electrical specifications.
2. General description
The PN512 is a highly integrated transceiver IC for contactless communication at
13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation
concept completely integrated for different kinds of contactless communication methods
and protocols at 13.56 MHz.
The PN512 transceiver ICs support 4 different operating modes
• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• Reader/Writer mode supporting ISO/IEC 14443B
• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• NFCIP-1 mode
Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal
transmitter part is able to drive a reader/writer antenna designed to communicate with
ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The
receiver part provides a robust and efficient implementation of a demodulation and
decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and
transponders. The digital part handles the complete ISO/IEC 14443A framing and error
detection (Parity & CRC).
The PN512 supports MIFARE 1 KB or MIFARE 4 KB emulation products. The PN512
supports contactless communication using MIFARE higher transfer speeds up to
424 kbit/s in both directions.
Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN512 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication
scheme, given correct implementation of additional components, like oscillator, power
supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4
and/or ISO/IEC 14443B anticollision are correctly implemented.
1 page  
NXP Semiconductors
6. Block diagram
PN512www.DataSheet4U.com
Transmission Module
PUBLIC
The Analog interface handles the modulation and demodulation of the analog signals
according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare
the internal receiver to demodulate signals, which are sent to the PN512.
The communication (S2C) interface provides digital signals to support communication for
transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC.
The contactless UART handles the protocol requirements for the communication schemes
in co-operation with the host controller. The comfortable FIFO-buffer allows a fast and
convenient data transfer from the host controller to the contactless UART and vice versa.
Various host controller interfaces are implemented to fulfill different customer
requirements.
Registerbank
I²C
8bit parallel
Interface
UART
SPI
FIFO
Serial
Signal
Switch
Data Mode
Detector
Contactless
UART
RF Level
Detector
Analog
Interface
Host Controller
interface
S²C
Fig 1. Simplified PN512 Block diagram
111334
Product data sheet
Rev. 3.4 — 8 September 2009
© NXP B.V. 2010. All rights reserved.
5 of 131
5 Page 
NXP Semiconductors
PN512www.DataSheet4U.com
Transmission Module
PUBLIC
Table 5. PN512 registers overview …continued
Addr Register Name Function
(hex)
0 PageReg
Selects the register page
1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation
2
3
GsNOffReg
Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation, when the driver is switched off
4 ModWidthReg Controls the setting of the ModWidth
5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit
6 RFCfgReg Configures the receiver gain and RF level
7
GsNOnReg
Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation when the drivers are switched on
8
CWGsPReg
Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during times of no modulation
9
ModGsPReg
Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during modulation
A TModeReg Defines settings for the internal timer
B TPrescalerReg
C
TReloadReg
Describes the 16-bit timer reload value
D
E TCounterValReg Shows the 16-bit actual timer value
F
Page 3: TestRegister
0 PageReg
selects the register page
1
TestSel1Reg
General test signal configuration
2
TestSel2Reg
General test signal configuration and PRBS control
3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial
interfaces only)
4 TestPin
ValueReg
Defines the values for the 8-bit parallel bus when it is used as I/O bus
5
TestBusReg
Shows the status of the internal testbus
6
AutoTestReg
Controls the digital selftest
7
VersionReg
Shows the version
8 AnalogTestReg Controls the pins AUX1 and AUX2
9 TestDAC1Reg Defines the test value for the TestDAC1
A TestDAC2Reg Defines the test value for the TestDAC2
B
TestADCReg
Shows the actual value of ADC I and Q
C-F RFT
Reserved for production tests
111334
Product data sheet
Rev. 3.4 — 8 September 2009
© NXP B.V. 2010. All rights reserved.
11 of 131
11 Page | ||
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| PDF Descargar | [ Datasheet PN512.PDF ] | |
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