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Teilenummer | ADC12D1800 |
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Beschreibung | Single 3.6 GSPS ADC | |
Hersteller | National Semiconductor | |
Logo | ||
Gesamt 14 Seiten ADC12D1800
PRODUCT BRIEF
www.DataSheet4U.com
PRELIMINARY
May 18, 2010
12-Bit, Single 3.6 GSPS ADC
1.0 General Description
The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in
National's Ultra-High-Speed ADC family and builds upon the
features, architecture and functionality of the 10-bit GHz fam-
ily of ADCs.
The ADC12D1800 provides a flexible LVDS interface which
has multiple SPI programmable options to facilitate board de-
sign and FPGA/ASIC data capture. The LVDS outputs are
compatible with IEEE 1596.3-1996 and supports pro-
grammable common mode voltage.
The product is packaged in a leaded or lead-free 292-ball
thermally enhanced BGA package over the rated industrial
temperature range of -40°C to +85°C.
Notice: This document is not a full datasheet. For more
information regarding this product or to order samples
please contact your local National Semiconductor sales
office or visit http://www.national.com/support/dir.html
2.0 Applications
■ Wideband Communications
■ Data Acquisition Systems
■ RADAR/LIDAR
■ Set-top Box
■ Consumer RF
■ Software Defined Radio
3.0 Features
■ Configurable to either 3.6 GSPS interleaved or 1.8 GSPS
dual ADC
■ Pin-compatible with ADC10D1000/1500 and
ADC12D1000/1600
■ Internally terminated, buffered, differential analog inputs
■ Interleaved timing automatic and manual skew adjust
■ Test patterns at output for system debug
■ Programmable 15-bit gain and 12-bit plus sign offset
■ Programmable tAD adjust feature
■ 1:1 non-demuxed or 1:2 demuxed LVDS outputs
■ AutoSync feature for multi-chip systems
■ Single power supply
4.0 Key Specifications
■ Resolution
Interleaved 3.6 GSPS ADC
■ Noise Floor
■ IMD3
■ Noise Power Ratio
■ Power
■ Full Power Bandwidth
Dual 1.8 GSPS ADC, Fin = 125MHz
■ ENOB
■ SNR
■ SFDR
■ Power
■ Full Power Bandwidth
12 Bits
-147 dBm/Hz (typ)
-61 dBFS (typ)
52 dB (typ)
4.1W (typ)
2.15 GHz (typ)
9.2 (typ)
57.8 dB (typ)
67 dBc (typ)
4.1W (typ)
2.8 GHz (typ)
5.0 Block Diagram
© 2010 National Semiconductor Corporation 301232
30123211
www.national.com
Ball No.
Name
Y4/W5
RCLK+/-
Y5/U6
V6/V7
RCOut1+/-
RCOut2+/-
Equivalent Circuit
Description
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Reference Clock Input. When the AutoSync
feature is active, and the ADC12D1800 is in
Slave Mode, the internal divided clocks are
synchronized with respect to this input clock. The
delay on this clock may be adjusted when
synchronizing multiple ADCs. This feature is
available in ECM via Control Register (Addr:
Eh).
Reference Clock Output 1 and 2. These signals
provide a reference clock at a rate of CLK/4,
when enabled, independently of whether the
ADC is in Master or Slave Mode. They are used
to drive the RCLK of another ADC12D1800, to
enable automatic synchronization for multiple
ADCs (AutoSync feature). The impedance of
each trace from RCOut1 and RCOut2 to
the RCLK of another ADC12D1800 should be
100Ω differential. Having two clock outputs
allows the auto-synchronization to propagate as
a binary tree. Use the DOC Bit (Addr: Eh, Bit 1)
to enable/ disable this feature; default is disabled.
www.national.com
6
6 Page Ball No.
J18/J19
H19/H20
H17/H18
G19/G20
G17/G18
F18/F19
E19/E20
D19/D20
D18/E18
C19/C20
B19/B20
B18/C17
·
M18/M19
N19/N20
N17/N18
P19/P20
P17/P18
R18/R19
T19/T20
U19/U20
U18/T18
V19/V20
W19/W20
W18/V17
A18/A19
B17/C16
A16/B16
B15/C15
C14/D14
A14/B14
B13/C13
C12/D12
A12/B12
B11/C11
C10/D10
A10/B10
·
Y18/Y19
W17/V16
Y16/W16
W15/V15
V14/U14
Y14/W14
W13/V13
V12/U12
Y12/W12
W11/V11
V10/U10
Y10/W10
Name
DI11+/-
DI10+/-
DI9+/-
DI8+/-
DI7+/-
DI6+/-
DI5+/-
DI4+/-
DI3+/-
DI2+/-
DI1+/-
DI0+/-
·
DQ11+/-
DQ10+/-
DQ9+/-
DQ8+/-
DQ7+/-
DQ6+/-
DQ5+/-
DQ4+/-
DQ3+/-
DQ2+/-
DQ1+/-
DQ0+/-
DId11+/-
DId10+/-
DId9+/-
DId8+/-
DId7+/-
DId6+/-
DId5+/-
DId4+/-
DId3+/-
DId2+/-
DId1+/-
DId0+/-
·
DQd11+/-
DQd10+/-
DQd9+/-
DQd8+/-
DQd7+/-
DQd6+/-
DQd5+/-
DQd4+/-
DQd3+/-
DQd2+/-
DQd1+/-
DQd0+/-
Equivalent Circuit
Description
www.DataSheet4U.com
I- and Q-channel Digital Data Outputs. In Non-
Demux Mode, this LVDS data is transmitted at
the sampling clock rate. In Demux Mode, these
outputs provide ½ the data at ½ the sampling
clock rate, synchronized with the delayed data,
i.e. the other ½ of the data which was sampled
one clock cycle earlier. Compared with the DId
and DQd outputs, these outputs represent the
later time samples. If used, each of these outputs
should always be terminated with a 100Ω
differential resistor placed as closely as possible
to the differential receiver.
Delayed I- and Q-channel Digital Data Outputs.
In Non-Demux Mode, these outputs are tri-
stated. In Demux Mode, these outputs provide ½
the data at ½ the sampling clock rate,
synchronized with the non-delayed data, i.e. the
other ½ of the data which was sampled one clock
cycle later. Compared with the DI and DQ
outputs, these outputs represent the earlier time
samples. If used, each of these outputs should
always be terminated with a 100Ω differential
resistor placed as closely as possible to the
differential receiver.
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12
12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ ADC12D1800 Schematic.PDF ] |
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