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PDF ADC12D1600 Data sheet ( Hoja de datos )
| Número de pieza | ADC12D1600 | |
| Descripción | (ADC12D1000 / ADC12D1600) 2.0/3.2 GSPS Ultra High-Speed ADC | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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ADC12D1000/ADC12D1600
PRODUCT BRIEF
www.DataSheet4U.com
PRELIMINARY
May 18, 2010
12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC
1.0 General Description
The 12-bit, 2.0/3.2 GSPS ADC12D1000/1600 is the latest ad-
vance in National's Ultra High-Speed ADC family and builds
upon the features, architecture and functionality of the 10-bit
GHz family of ADCs.
The ADC12D1000/1600 provides a flexible LVDS interface
which has multiple SPI programmable options to facilitate
board design and FPGA/ASIC data capture. The LVDS out-
puts are compatible with IEEE 1596.3-1996 and support pro-
grammable common mode voltage.
The ADC12D1000/1600 is packaged in a leaded or lead-free
292-ball thermally enhanced BGA package over the rated in-
dustrial temperature range of -40°C to +85°C.
Notice: This document is not a full datasheet. For more
information regarding this product or to order samples
please contact your local National Semiconductor sales
office or visit http://www.national.com/support/dir.html
2.0 Applications
■ Wideband Communications
■ Data Acquisition Systems
■ RADAR/LIDAR
■ Set-top Box
■ Consumer RF
■ Software Defined Radio
3.0 Features
■ Configurable to either 2.0/3.2 GSPS interleaved or 1.0/1.6
GSPS dual ADC
■ Pin-compatible with ADC10D1000/1500
■ Internally terminated, buffered, differential analog inputs
■ Interleaved timing automatic and manual skew adjust
■ Test patterns at output for system debug
■ Programmable 15-bit gain and 12-bit plus sign offset
■ Programmable tAD adjust feature
■ 1:1 non-demuxed or 1:2 demuxed LVDS outputs
■ AutoSync feature for multi-chip systems
■ Single 1.9V ± 0.1V power supply
4.0 Key Specifications
■ Resolution
12 Bits
Interleaved 2.0/3.2 GSPS ADC
■ Noise Floor
■ IMD3
■ Noise Power Ratio
■ Power
■ Full Power Bandwidth
-147.5/-147.5 dBm/Hz (typ)
-66/-63 dBFS (typ)
52/52 dB (typ)
3.4/3.8W (typ)
2.15/2.15 GHz (typ)
Dual 1.0/1.6 GSPS ADC, Fin = 125 MHz
■ ENOB
■ SNR
■ SFDR
■ Power
■ Full Power Bandwidth
9.5/9.3 Bits (typ)
59.1/58.6 dB (typ)
70.5/68 dBc (typ)
3.4/3.8W (typ)
2.8/2.8GHz (typ)
5.0 Simplified Block Diagram
© 2010 National Semiconductor Corporation 300916
30091611
www.national.com
1 page  
Ball No.
Name
C2 VCMO
B1 VBG
C3/D3
Rext+/-
C1/D2
Rtrim+/-
E2/F3
Tdiode+/-
Equivalent Circuit
Description
www.DataSheet4U.com
Common Mode Voltage Output or Signal
Coupling Select. If AC-coupled operation at the
analog inputs is desired, this pin should be held
at logic-low level. This pin is capable of sourcing/
sinking up to 100 µA. For DC-coupled operation,
this pin should be left floating or terminated into
high-impedance. In DC-coupled Mode, this pin
provides an output voltage which is the optimal
common-mode voltage for the input signal and
should be used to set the common-mode voltage
of the driving buffer.
Bandgap Voltage Output or LVDS Common-
mode Voltage Select. This pin provides a
buffered version of the bandgap output voltage
and is capable of sourcing/sinking 100 uA and
driving a load of up to 80 pF. Alternately, this pin
may be used to select the LVDS digital output
common-mode voltage. If tied to logic-high, the
1.2V LVDS common-mode voltage is selected;
0.8V is the default.
External Reference Resistor terminals. A 3.3 kΩ
±0.1% resistor should be connected between
Rext+/-. The Rext resistor is used as a reference
to trim internal circuits which affect the linearity of
the converter; the value and precision of this
resistor should not be compromised.
Input Termination Trim Resistor terminals. A 3.3
kΩ ±0.1% resistor should be connected between
Rtrim+/-. The Rtrim resistor is used to establish
the calibrated 100Ω input impedance of VinI,
VinQ and CLK. These impedances may be fine
tuned by varying the value of the resistor by a
corresponding percentage; however, the tuning
range and performance is not guaranteed for
such an alternate value.
Temperature Sensor Diode Positive (Anode) and
Negative (Cathode) Terminals. This set of pins is
used for die temperature measurements. It has
not been fully characterized.
5 www.national.com
5 Page 
Ball No.
K19/K20
L19/L20
Name
DCLKI+/-
DCLKQ+/-
TABLE 4. High-Speed Digital Outputs
Equivalent Circuit
Description
www.DataSheet4U.com
Data Clock Output for the I- and Q-channel data
bus. These differential clock outputs are used to
latch the output data and, if used, should always
be terminated with a 100Ω differential resistor
placed as closely as possible to the differential
receiver. Delayed and non-delayed data outputs
are supplied synchronously to this signal. In 1:2
Demux Mode or Non-Demux Mode, this signal is
at ¼ or ½ the sampling clock rate, respectively.
DCLKI and DCLKQ are always in phase with
each other, unless one channel is powered down,
and do not require a pulse from DCLK_RST to
become synchronized.
K17/K18
L17/L18
ORI+/-
ORQ+/-
Out-of-Range Output for the I- and Q-channel.
This differential output is asserted logic-high
while the over- or under-range condition exists,
i.e. the differential signal at each respective
analog input exceeds the full-scale value. Each
OR result refers to the current Data, with which it
is clocked out. If used, each of these outputs
should always be terminated with a 100Ω
differential resistor placed as closely as possible
to the differential receiver.
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADC12D1600.PDF ] | |
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