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P89V52X2 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89V52X2
Beschreibung 8-bit 80C51 low power 8 kB fash microcontrolle
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P89V52X2 Datasheet, Funktion
www.DataSheet4U.com
P89V52X2
8-bit 80C51 low power 8 kB flash microcontroller with 256 B
RAM, 192 B data EEPROM
Rev. 03 — 4 May 2009
Product data sheet
1. General description
The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and
192 B of data EEPROM. This device is designed to be a drop in and software compatible
replacement for the P87C52, P87C52X2, P89C52, and P89C52X2 devices.
2. Features
2.1 Principal features
I 0 MHz to 40 MHz operating frequency in 12× mode, 20 MHz in 6× mode
I 8 kB of on-chip flash user code memory
I 256 B of RAM
I Enhanced UART
I Three 16-bit timers/counters
I Four 8-bit I/O ports
I Supports 12-clock (default) or 6-clock mode selection via software or In-Circuit
Programming (ICP)
I DIP40, PLCC44, and LQFP44 packages
I Six interrupt sources with four priority levels
I Second DPTR register
2.2 Additional features
I Very low power
I Low EMI mode (ALE inhibit)
I Power-down mode with external interrupt wake-up
I Idle mode
I Extended temperature range
I Three security bits
I Programmable clock-out pin






P89V52X2 Datasheet, Funktion
NXP Semiconductors
www.DataSheet4U.com
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
Table 2. Pin description …continued
Symbol
Pin
DIP40 LQFP44
P1[7]
83
P2[0] to P2[7]
PLCC44
9
P2[0]/A8
21
18
24
P2[1]/A9
22
19
25
P2[2]/A10
23
20
26
P2[3]/A11
24
21
27
P2[4]/A12
25
22
28
P2[5]/A13
26
23
29
P2[6]/A14
27
24
30
P2[7]/A15
28
25
31
P3[0] to P3[7]
P3[0]/RXD
10
5
11
P3[1]/TXD
11
7
13
P3[2]/INT0
12
8
14
P3[3]/INT1
13
9
15
P3[4]/T0 14 10 16
Type
I/O
I/O with
internal
pull-up
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
with
internal
pull-up
I
I
O
O
I
I
I
I
I/O
I
Description
P1[7] — Port 1 bit 7.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 2 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups. Port 2 sends the high-order address
byte during fetches from external program memory and
during accesses to external Data Memory that use 16-bit
address (MOVX@DPTR). In this application, it uses strong
internal pull-ups when transitioning to ‘1’s.
P2[0] — Port 2 bit 0.
A8 — Address bit 8.
P2[1] — Port 2 bit 1.
A9 — Address bit 9.
P2[2] — Port 2 bit 2.
A10 — Address bit 10.
P2[3] — Port 2 bit 3.
A11 — Address bit 11.
P2[4] — Port 2 bit 4.
A12 — Address bit 12.
P2[5] — Port 2 bit 5.
A13 — Address bit 13.
P2[6] — Port 2 bit 6.
A14 — Address bit 14.
P2[7] — Port 2 bit 7.
A15 — Address bit 15.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 3 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups.
P3[0] — Port 3 bit 0.
RXD — Serial input port.
P3[1] — Port 3 bit 1.
TXD — Serial output port.
P3[2] — Port 3 bit 2.
INT0 — External interrupt 0 input.
P3[3] — Port 3 bit 3.
INT1 — External interrupt 1 input
P3[4] — Port 3 bit 4.
T0 — External count input to Timer/Counter 0.
P89V52X2_3
Product data sheet
Rev. 03 — 4 May 2009
© NXP B.V. 2009. All rights reserved.
6 of 57

6 Page









P89V52X2 pdf, datenblatt
NXP Semiconductors
www.DataSheet4U.
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
C2
XTAL2
XTAL1
C1
VSS
002aaa545
Fig 5. Oscillator characteristics (using the on-chip oscillator)
n.c. XTAL2
external
oscillator
signal
XTAL1
VSS
002aaa546
Fig 6. Oscillator characteristics (external clock drive)
6.3.2 Clock control register (CKCON)
By default, the device runs at twelve clocks per machine cycle. The device may be run in 6
clock per machine cycle mode by programming of either a non-volatile bit (FX2) or an SFR
bit (Table 5 “Clock modes”). If the FX2 non-volatile bit is programmed the device will run in
6-clock mode and the X2 SFR bit has no effect. If the FX2 bit is erased, then the clock
mode is controlled by the X2 SFR bit.
Table 5. Clock modes
FX2 clock mode bit (UCFG.1) X2 bit (CLKCON.0)
erased
0
erased
1
programmed
x
CPU clock mode
12-clock mode (default)
6-clock mode
6-clock mode
6.4 ALE control
Table 6. AUXR - Auxiliary register (address 8EH) bit allocation
Not bit addressable; Reset value 00H
Bit 7 6 5 4 3 2
Symbol
-
-
-
-
-
-
10
- AO
P89V52X2_3
Product data sheet
Rev. 03 — 4 May 2009
© NXP B.V. 2009. All rights reserved.
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