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P89LPC972 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89LPC972
Beschreibung 8-bit microcontroller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 66 Seiten
P89LPC972 Datasheet, Funktion
www.DataSheet4U.com
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
2 kB/4 kB/8 kB wide-voltage byte-erasable flash
Rev. 02 — 27 April 2010
Product data sheet
1. General description
The P89LPC970/971/972 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC970/971/972 in order to reduce component
count, board space, and system cost.
2. Features and benefits
2.1 Principal features
„ 2 kB/4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and
64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data
storage.
„ 256-byte RAM data memory.
„ Two analog comparators with selectable inputs and reference source.
„ Five 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
„ A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
„ Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port.
„ SPI communication port (pin remap).
„ High-accuracy internal RC oscillator option 7.373 MHz calibrated to ±1 %, with clock
doubler option, allows operation without external oscillator components. The RC
oscillator option is selectable and fine tunable.
„ Watchdog timer with separate on-chip oscillator, nominal 400 kHz/25 kHz, calibrated to
±10 % at 400 kHz, requiring no external components. The watchdog prescaler is
selectable from eight values.
„ Pin remap for UART, I2C-bus and SPI.
„ 2.4 V to 5.5 V VDD operating range.
„ Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
„ 20-pin TSSOP and DIP packages with 15 I/O pins minimum and up to 18 I/O pins
while using on-chip oscillator and reset options.






P89LPC972 Datasheet, Funktion
NXP Semiconductors
6. Pinning information
6.1 Pinning
www.DataSheet4U.com
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
P0.0/CMP2/KBI0/SPICLK 1
P1.7/T3EX/MOSI 2
P1.6/MISO 3
P1.5/RST 4
VSS 5
P3.1/XTAL1 6
P3.0/XTAL2/CLKOUT 7
P1.4/INT1/T4EX/SS 8
P1.3/INT0/SDA/T4 9
P1.2/SCL/T0 10
P89LPC970/971/972
20 P0.1/CIN2B/KBI1
19 P0.2/CIN2A/KBI2
18 P0.3/CIN1B/KBI3/T2
17 P0.4/CIN1A/KBI4
16 P0.5/CMPREF/KBI5/T3
15 VDD
14 P0.6/CMP1/KBI6
13 P0.7/KBI7/T1
12 P1.0/TXD
11 P1.1/RXD/T2EX
002aae552
Fig 3. TSSOP20 pin configuration
P89LPC970/971/972
P0.0/CMP2/KBI0/SPICLK 1
P1.7/T3EX/MOSI 2
P1.6/MISO 3
P1.5/RST 4
VSS 5
P3.1/XTAL1 6
P3.0/XTAL2/CLKOUT 7
P1.4/INT1/T4EX/SS 8
P1.3/INT0/SDA/T4 9
P1.2/SCL/T0 10
20 P0.1/CIN2B/KBI1
19 P0.2/CIN2A/KBI2
18 P0.3/CIN1B/KBI3/T2
17 P0.4/CIN1A/KBI4
16 P0.5/CMPREF/KBI5/T3
15 VDD
14 P0.6/CMP1/KBI6
13 P0.7/KBI7/T1
12 P1.0/TXD
11 P1.1/RXD/T2EX
002aae553
Fig 4. P89LPC972 DIP20 pin configuration
P89LPC97X_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 April 2010
© NXP B.V. 2010. All rights reserved.
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Table 4. Special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
MSB
LSB
Reset value
Hex Binary
FMCON Program flash
E4H BUSY
-
-
-
HVA
HVE
SV
OI 70 0111 0000
control (Read)
Program flash
control (Write)
E4H FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.
76543210
FMDATA Program flash
data
E5H
00 0000 000
0
I2ADR
I2C-bus slave
address register
DBH
I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0
GC 00
0000 000
0
Bit address DF DE DD DC DB DA D9 D8
I2CON* I2C-bus control
D8H
-
I2EN STA STO
SI
AA
register
- CRSEL 00 x000 00x0
I2DAT
I2C-bus data
register
DAH
I2SCLH
Serial clock
generator/SCL
duty cycle
register high
DDH
00 0000 000
0
I2SCLL
Serial clock
generator/SCL
duty cycle
register low
DCH
00 0000 000
0
I2STAT I2C-bus status
D9H
STA.4 STA.3 STA.2 STA.1 STA.0
0
0
0 F8 1111 1000
register
Bit address AF AE AD AC AB AA A9 A8
IEN0*
Interrupt
enable 0
A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 000
0
Bit address EF EE ED EC EB EA E9 E8
IEN1*
Interrupt
enable 1
E8H
-
EST
-
EXTIM ESPI
EC
EKBI
EI2C 00[2] 00x0 0000
Bit address BF BE BD BC BB BA B9 B8
IP0* Interrupt
priority 0
B8H
- PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[2] x000 0000
IP0H
Interrupt
priority 0 high
B7H
-
PWDRTH PBOH PSH/
PT1H
PX1H
PT0H
PX0H 00[2] x000 0000
PSRH

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