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PDF EP80579 Data sheet ( Hoja de datos )

Número de pieza EP80579
Descripción Integrated Processor Product Line
Fabricantes Intel　
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No Preview Available ! EP80579 Hoja de datos, Descripción, Manual

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Intel® EP80579 Integrated Processor
Product Line
Datasheet
Order Number: 320066-003US
August 2009

1 page




EP80579 pdf
Contents
www.DataSheet4U.com
5.2.1 Hardware Capabilities ............................................................................. 139
5.2.2 Software Usage Model ............................................................................ 141
5.3 Error Reporting by the IMCH ............................................................................. 141
5.3.1 Overview of the First and Next Error Architecture ....................................... 141
5.3.2 Global Error Events ................................................................................ 142
5.3.3 Unit-Level Errors from the Buffer Unit ....................................................... 143
5.3.4 Unit-Level Errors from the DRAM Interface ................................................ 143
5.3.5 Unit-Level Errors from the FSB Interface ................................................... 144
5.3.6 Unit-Level Errors from the NSI ................................................................. 145
5.3.7 Unit-Level Errors from the EDMA Engine.................................................... 146
5.3.8 Unit-Level Errors from PCI Express* Ports A0 and A1 .................................. 147
5.4 Error Reporting by the IICH .............................................................................. 149
5.4.1 SMBus Interface .................................................................................... 149
5.4.2 LPC Interface......................................................................................... 150
5.4.3 USB 1.1 Interface .................................................................................. 151
5.4.4 USB 2.0 Interface .................................................................................. 151
5.4.5 SATA Interface ...................................................................................... 152
5.4.6 Serial I/O Interface ................................................................................ 153
5.5 Error Reporting by the System Memory Controller ............................................... 153
5.5.1 Handling Out-of-Bounds Addresses........................................................... 154
5.5.2 IMCH - Memory Controller ....................................................................... 154
5.6 Error Reporting by AIOC Devices ....................................................................... 155
5.6.1 Gigabit Ethernet MAC ............................................................................. 155
5.6.2 CAN Interface ........................................................................................ 156
5.6.3 SSP Interface ........................................................................................ 157
5.6.4 Local Expansion Bus ............................................................................... 158
5.6.5 IEEE 1588, and GCU............................................................................... 159
6.0 Reset and Power Management............................................................................... 161
6.1 Reset and Powergood Distribution ..................................................................... 161
6.1.1 Types of Reset....................................................................................... 161
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.1.6
Powergood Implementation.............................................................. 161
Hard Reset Implementation.............................................................. 162
Software Controlled Reset................................................................ 162
CPU Only Reset Implementation ....................................................... 162
S-state Wake Events ....................................................................... 163
Targeted Reset Implementation ........................................................ 163
6.1.2 Platform Reset and Powergood................................................................. 163
6.1.2.1
6.1.2.2
6.1.2.3
Platform Powergood ........................................................................ 163
Platform Reset................................................................................ 163
Reset and Powergood Distribution ..................................................... 164
6.1.3 EP80579 Power Sequencing and Reset Sequence........................................ 167
6.2 BIOS Boot Flow (Initialization) .......................................................................... 175
6.2.1 Memory Configuration............................................................................. 176
6.2.2 Memory Initialization .............................................................................. 176
6.2.3 Boot from Network ................................................................................. 176
6.3 Power Management ......................................................................................... 177
6.3.1 Power Management States ...................................................................... 177
6.3.2 Power Management Support .................................................................... 179
6.3.2.1
6.3.2.2
Transitioning Between Power States .................................................. 181
Power State Transition Timing Diagrams ............................................ 181
6.3.3 Thermal Sensor ..................................................................................... 182
6.3.4 ACPI Implementation.............................................................................. 182
7.0 Register Summary ................................................................................................. 183
7.1 Overview of Register Descriptions and Summaries ............................................... 183
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
5

5 Page





EP80579 arduino
Contents
www.DataSheet4U.com
15.3.1 Supported System Power States .............................................................. 380
15.3.1.1 Supported CPU Power States ............................................................ 381
15.3.1.2 Supported Device Power States ........................................................ 381
15.3.1.3 Supported Bus Power States ............................................................ 381
15.3.2 DDR2 Interface Power Management.......................................................... 381
15.3.3 PCI Express Interface Power Management ................................................. 382
15.3.3.1 PCI Express Link Power State Definitions ........................................... 382
15.3.3.2 Software Controlled PCI Express Link States....................................... 382
15.3.3.3 Hardware Controlled PCI Express Link States...................................... 383
15.3.3.4 System Clocking Solution Dependencies............................................. 384
15.3.3.5 Device and Link PM Initialization ....................................................... 384
15.3.4 Device and Slot Power Limits ................................................................... 385
15.3.5 PME Support.......................................................................................... 385
15.3.5.1 PME Wake Signaling ........................................................................ 385
15.3.5.2 PME Messaging............................................................................... 386
15.3.6 BIOS Support for PCI Express PM Messaging.............................................. 386
15.3.6.1 PCI Express PME_TURN_OFF Semantic .............................................. 386
16.0 IMCH Registers...................................................................................................... 389
16.1 IMCH Registers: Bus 0, Device 0, Function 0 ...................................................... 389
16.1.1 Register Details ..................................................................................... 391
16.1.1.1
16.1.1.2
16.1.1.3
16.1.1.4
16.1.1.5
16.1.1.6
16.1.1.7
16.1.1.8
16.1.1.9
16.1.1.10
16.1.1.11
16.1.1.12
16.1.1.13
16.1.1.14
16.1.1.15
16.1.1.16
16.1.1.17
16.1.1.18
16.1.1.19
16.1.1.20
16.1.1.21
16.1.1.22
16.1.1.23
16.1.1.24
16.1.1.25
16.1.1.26
16.1.1.27
16.1.1.28
16.1.1.29
16.1.1.30
16.1.1.31
16.1.1.32
16.1.1.33
Offset 00h: VID – Vendor Identification Register ................................. 391
Offset 02h: DID – Device Identification Register ................................. 391
Offset 04h: PCICMD: PCI Command Register ...................................... 392
Offset 06h: PCISTS: PCI Status Register ............................................ 393
Offset 08h: RID - Revision Identification Register ................................ 394
Offset 0Ah: SUBC - Sub-Class Code Register ...................................... 394
Offset 0Bh: BCC – Base Class Code Register....................................... 394
Offset 0Eh: HDR - Header Type Register ............................................ 395
Offset 14h: SMRBASE - System Memory RCOMP Base
Address Register............................................................................. 395
Offset 2Ch: SVID - Subsystem Vendor Identification Register ............... 396
Offset 2Eh: SID - Subsystem Identification Register ............................ 397
Offset 4Ch: NSIBAR - Root Complex Block Address Register ................. 397
Offset 50h: CFG0 - IMCH Configuration 0 Register............................... 398
Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register ..................... 399
Offset 53h: CFGNS1 - Configuration 1 Register ................................... 399
Offset 58h: FDHC - Fixed DRAM Hole Control Register ......................... 400
Offset 59h: PAM0 - Programmable Attribute Map 0 Register ................. 401
Offset 5Ah: PAM1 - Programmable Attribute Map 1 Register ................. 402
Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register ................. 403
Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register ................. 404
Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register ................. 405
Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register ................. 406
Offset 5Fh: PAM6 - Programmable Attribute Map 6 Register.................. 407
Offset 9Ch: DEVPRES - Device Present Register .................................. 407
Offset 9Dh: EXSMRC - Extended System Management RAM Control Register.
409
Offset 9Eh: SMRAM - System Management RAM Control Register .......... 411
Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control
Register ........................................................................................ 413
Offset B8h: IMCH_MENCBASE - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Base Address Register ......................................................... 413
Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Limit Address Register......................................................... 414
Offset C4h: TOLM - Top of Low Memory Register................................. 414
Offset C6h: REMAPBASE - Remap Base Address Register...................... 416
Offset C8h: REMAPLIMIT – Remap Limit Address Register .................... 416
Offset CAh: REMAPOFFSET - Remap Offset Register ............................ 417
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
11

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