PDF ADN2855 Data sheet ( Hoja de datos )

Número de pieza	ADN2855
Descripción	Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock And Data Recovery IC
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializer ADN2855 FEATURES Serial data input 155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps 12-bit acquisition time 4-bit parallel LVDS output interface Patented dual-loop clock recovery architecture Integrated PRBS generator Byte rate reference clock Loss-of-lock indicator Supports double data rate (DDR)-compatible FPGA I2C interface to access optional features Single-supply operation: 3.3 V Power 670 mW typical in serial output mode 825 mW typical in deserializer mode 5 mm × 5 mm, 32-lead LFCSP APPLICATIONS Passive optical networks GPON/BPON/GEPON OLT receivers GENERAL DESCRIPTION The ADN2855 is a burst mode clock and data recovery IC designed for GPON/BPON/GEPON optical line terminal (OLT) receiver applications. The part can operate at 155.52 Mbps, 622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable via the I2C interface. The ADN2855 frequency locks to the OLT reference clock and aligns to the input data within 12 bits of the start of the preamble. The device provides a full rate or an optional half rate output clock for a double data rate (DDR) interface to an FPGA or digital ASIC. All specifications are quoted for −40°C to +85°C ambient tempera- ture, unless otherwise noted. The ADN2855 is available in a compact 5 mm × 5 mm, 32-lead chip scale package. FUNCTIONAL BLOCK DIAGRAM REFCLKP, REFCLKN DATAV CF1 CF2 VCC VEE RESET ADN2855 FREQUENCY/ LOCK DETECT LOOP FILTER PIN CML INPUT BUFFER NIN PHASE SHIFTER PHASE DETECT LOOP FILTER DATA RE-TIMING 2 DESERIALIZER DIVIDER VCO SDA I2C SCK 4×2 DATxP, DATxN 2 CLKOUTP, CLKOUTN Figure 1. SQUELCH Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 1 page TIMING CHARACTERISTCS CLKOUTP DATxP/ DATxN OUTP OUTN OUTP – OUTN 0V VLVDS VSE tS tH Figure 2. Output Timing VDIFF Figure 3. Single-Ended vs. Differential Output Specifications CLKOUTP DAT0P/ DAT0N tS tH Figure 4. Serial Output Mode (Full Rate Clock) CLKOUTP DAT0P/ DAT0N tS tH Figure 5. Serial Output Mode (Half Rate Clock, DDR Mode) CLKOUTP DATxP/ DATxN tS tH Figure 6. Nibble Output Mode (Full Rate Clock) CLKOUTP DATxP/ DATxN tS tH Figure 7. Nibble Output Mode (Half Rate Clock, DDR Mode) ADN2855www.DataSheet4U.com VSE Rev. 0 \| Page 5 of 20 5 Page THEORY OF OPERATION The ADN2855 is designed specifically for burst mode data recovery in GPON/BPON/GEPON optical line terminal (OLT) receivers. The ADN2855 requires a reference clock that is frequency locked to the incoming data. The FLL (frequency-locked loop) of the ADN2855 acquires frequency lock with respect to this reference clock, pulling the VCO towards 0 ppm frequency error. It is assumed that the upstream bursts to the OLT are clocked by the recovered clock from the optical network terminal (ONT) CDR. This guarantees frequency lock to the OLT system clock. The ADN2855 has a preamble detector that looks for a maximum transition density pattern (1010…) within the preamble. Once this pattern is detected in the preamble, the on-chip delay/phase- locked loop (D/PLL) quickly acquires phase lock to the incoming ADN2855www.DataSheet4U.com burst within 12 UI of the 1010… pattern. The D/PLL also pulls in any remaining frequency error that was not pulled in by the FLL. The incoming data is retimed by the recovered clock and output either serially or in a 4-bit parallel output nibble. The ADN2855 requires a RESET signal between bursts to set the device into a fast phase acquisition mode. The RESET signal must be asserted within 8 UI of the end of the previous burst, and it must be deasserted prior to the start of the maximum transition density portion of the preamble, which is specifically provided for the burst mode clock recovery device to acquire the phase of the incoming burst. The RESET signal must be at least 16 UI wide. See the Reset Timing Options section for more details. Rev. 0 \| Page 11 of 20 11 Page

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