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PDF ADA4320-1 Data sheet ( Hoja de datos )
| Número de pieza | ADA4320-1 | |
| Descripción | Low-distortion Upstream CATV Line Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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High Power, Low Distortion Upstreamwww.DataSheet4U.com
CATV Line Driver
ADA4320-1
FEATURES
Supports CableLabs® DOCSIS 3.0/2.0 and EuroDOCSIS
3.0/2.0 specifications for customer premises equipment
(CPE) upstream transmission
5 V single-supply operation
Excellent adjacent channel rejection performance
−66 dBc ACPR for a single QPSK channel
−63 dBc ACPR for 4× QAM64 channels
Gain programmable in 1 dB steps over a 59 dB range
Gain range: −27 dB to +32 dB
Current-scaled output stage
Low between-burst output noise level
−70 dB mV in 160 kHz bandwidth
Maintains constant output impedance in enable, disable,
and sleep conditions
Selectable low power modes
12 mA in Tx disable
12 μA in sleep mode (full power-down)
3-wire, SPI-compatible interface
4 mm × 5 mm 24-lead LFCSP, RoHS compliant
APPLICATIONS
DOCSIS 3.0 and EuroDOCSIS cable modems/E-MTAs
DOCSIS 3.0 set-top boxes
CATV telephony modems
Coaxial or twisted pair line drivers
GENERAL DESCRIPTION
The ADA4320-1 is a high power, ultralow distortion amplifier
designed for CATV reverse channel line driving. Its features and
specifications make the ADA4320-1 ideally suited for DOCSIS 3.0-
and EuroDOCSIS 3.0-based applications. Both gain and output
stage current are controlled via a 3-wire (SPI-compatible) interface.
A single 8-bit serial word selects one of four available supply
current presets and one of sixty gain codes.
The ADA4320-1 has been tailored to address both the high output
drive and stringent fidelity requirements of DOCSIS 3.0. The
part is able to maintain excellent adjacent channel rejection
performance over the full 5 MHz to 85 MHz range, even with
multiple bonded channels at maximum specified output levels.
The ADA4320-1 accepts a differential or single-ended input
signal. The output is specified for driving a single-ended 75 Ω
load through a 4:1 impedance transformer.
FUNCTIONAL BLOCK DIAGRAM
VIN–
VIN+
DIFF OR
SINGLE
INPUT
AMP
VERNIER
ZIN (SINGLE) = 320Ω
ZIN (DIFF) = 640Ω
ADA4320-1
ATTENUATION
CORE
POWER
AMP
8
DECODE
8
DATA LATCH
8
SHIFT
REGISTER
ZOUT DIFF =
300Ω
POWER-DOWN
LOGIC
VOUT+
VOUT–
RAMP
GND DATEN SDATA CLK
Figure 1.
TXEN SLEEP
The ADA4320-1 features an output driver stage that scales
quiescent current consumption according to gain setting. In
multichannel mode at maximum gain (32 dB), the device draws
260 mA from a single 5 V supply, enabling the high power,
ultralow distortion performance required by multiple DOCSIS 3.0
upstream channels. For lifeline E-MTA applications, the ADA4320-1
output stage current can be throttled via SPI commands, reducing
the power requirement for single-channel transmission by up to
30%. In transmit-disable mode, the ADA4320-1 draws only 12 mA.
The device also features a full power-down sleep mode that
further reduces current draw to12 μA typical.
The ADA4320-1 is packaged in a RoHS-compliant, 24-lead
exposed pad LFCSP and is rated for operation over the −40°C
to +85°C temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2010 Analog Devices, Inc. All rights reserved.
1 page  
TIMING REQUIREMENTS
Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.
Table 3.
Parameter
Clock Pulse Width (tWH)
Clock Period (tC)
Setup Time SDATA vs. Clock (tDS)
Setup Time DATEN vs. Clock (tES)
Hold Time SDATA vs. Clock (tDH)
Hold Time DATEN vs. Clock (tEH)
Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock
Min
16
32
5
16
5
3
ADA4320-1www.DataSheet4U.com
Typ Max
10
Unit
ns
ns
ns
ns
ns
ns
ns
tDS
SDATA
CLK
DATEN
TXEN
VALID DATA-WORD G1
MSB...LSB
tWH tC
VALID DATA-WORD G2
tES tEH
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
SDATA MSB
CLK
VALID DATA BIT
MSB – 1
tDS tDH
MSB – 2
Figure 3. SDATA Timing
Rev. 0 | Page 5 of 16
5 Page 
APPLICATIONS INFORMATION
GENERAL APPLICATIONS
The ADA4320-1 is primarily intended for use as the reverse
channel power amplifier (PA) in DOCSIS® 3.0 customer premises
equipment (CPE), including cable modems, E-MTAs, and
DOCSIS-enabled set-top boxes. The signals are typically QPSK or
QAM waveforms generated by the upstream modulator and DAC.
To sufficiently attenuate DAC images, a low-pass reconstruction
filter is recommended between the DAC output and the
ADA4320-1. A differential filter is preferred, and its output
impedance should match the 640 Ω input impedance of the
ADA4320-1.
Varying distances between the CPE and the cable modem
termination system (CMTS), as well as diplexers and splitters
that may exist in the signal path, require the amplifier to
provide a wide range of output power. The combination of a
high output level, excellent linearity, and 59 dB gain range of the
ADA4320-1 enables the CPE to overcome inline losses and
ensures adequate signal strength at the upstream termination.
CIRCUIT DESCRIPTION
In power-up mode, the ADA4320-1 comprises three analog
functions. The input amplifier (preamp) can be used single-ended
or balanced (differential). If the input is used in the balanced
configuration, it is imperative that the input signals be 180° out
of phase and of equal amplitude. A Vernier adjustment amplifier
controls the 1 dB gain steps.
The digital attenuator (DA) stage provides coarse adjustment in
6 dB steps. It also scales the current supplied to the output stage.
Both the preamp and DA are differential (balanced) to improve
power supply rejection and linearity.
The differential current is output from the DA to the output stage.
The output stage, with its 300 Ω balanced output impedance,
maintains proper matching to a 75 Ω load when used with a
2:1 (turns ratio) balun transformer.
PROGRAMMING
The ADA4320-1 is controlled via a unidirectional, 3-wire serial
interface (SPI-compatible) consisting of CLK, DATEN, and SDATA
signals. An 8-bit data-word containing the output stage current
level (Bits[7:6]) and desired gain code (Bits[5:0]) is clocked into
the SDATA port, MSB first.
The programmable current level (CL) range of the ADA4320-1 is
CL3 (highest) to CL0 (lowest). The programmable gain range is
+32 dB (Gain Code 60) to −27 dB (Gain Code 01), in steps of 1 dB
per least significant bit (LSB), providing a total gain range of 59 dB.
ADA4320-1www.DataSheet4U.com
Table 7. Data-Word for Setting Current and Gain Levels
Typical
Current
CL (mA)
Cain
CL[7:6] Gain[5:0] Code
(Bin) (Hex)
(Dec)
Typical
Gain (dB)
3 260 to 77 11
3C to 01 60 to 01 +32 to −27
2 235 to 73 10
3C to 01 60 to 01 +32 to −27
1 210 to 70 01
3C to 01 60 to 01 +32 to −27
0 180 to 65 00
3C to 01 60 to 01 +32 to −27
The sequence of loading the SDATA register starts on the falling
edge of the DATEN pin, which activates the CLK line. Data on
the SDATA line is clocked into the serial shift register on the
rising edge of CLK, MSB first. The data-word is latched into
the attenuator core on the rising edge of DATEN. Serial interface
timing for the ADA4320-1 is shown in Figure 2 and Figure 3.
CURRENT LEVEL AND GAIN ADJUSTMENT
Gain adjustment and current scaling allow the PA to achieve the
high output levels and linearity required for multiple-channel
DOCSIS 3.0 compliance, while offering significantly reduced
power consumption in single-channel and lifeline battery-backup
modes of operation.
There are two methods of adjusting the output stage current of
the ADA4320-1. The first is performed automatically, lowering
output current as attenuation is increased (gain is reduced).
As shown in Figure 23, for every 6 dB reduction in gain, output
stage current is decreased. At higher gain settings, this is more
pronounced. At maximum gain and maximum current level,
a step down of 6 dB reduces the supply current by 33%.
The second method, which allows the user to program one of
four preset current levels (CL3 to CL0) at any gain setting, is
shown by the individual traces in Figure 23.
300
CURRENT LEVEL 3
CURRENT LEVEL 2
CURRENT LEVEL 1
250
CURRENT LEVEL 0
GAIN
30
18
200 6
150 –6
100 –18
50 –30
0 12 24 36 48 60
GAIN CODE
Figure 23. Gain and Current Scaling
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADA4320-1.PDF ] | |
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