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PDF ADP195 Data sheet ( Hoja de datos )
| Número de pieza | ADP195 | |
| Descripción | High-Side Power Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Logic Controlled, High-Side Power Switch
with Reverse Current Blocking
ADP195
FEATURES
Ultralow on resistance (RDSON)
50 mΩ @ 3.6 V
55 mΩ @ 2.5 V
65 mΩ @ 1.8 V
100 mΩ @ 1.2 V
Input voltage range: 1.1 V to 3.6 V
1.1 A maximum continuous operating current
Low enable control logic threshold can be operated from
1.2 V to 3.3 V
Low 1 μA (typical) ground current @ 1.8 V
Low 4 μA (maximum) reverse current @ 3.6 V
Ultralow shutdown current: 0.7 μA (typical) @ 1.8 V
Reverse current blocking
Tiny 4-ball wafer level chip scale package (WLCSP)
1.0 mm × 1.0 mm, 0.5 mm pitch
Tiny 6-lead lead frame chip scale package (LFCSP)
2.0 mm × 2.0 mm × 0.55 mm, 0.65 mm pitch
APPLICATIONS
Mobile phones
Digital cameras and audio devices
GPS devices
Personal media players
Portable and battery-powered equipment
TYPICAL APPLICATIONS CIRCUIT
VIN
+
– GND
ADP195
REVERSE
POLARITY
PROTECTION
VOUT
ON
EN OFF
LEVEL SHIFT
AND SLEW
RATE CONTROL
LOAD
Figure 1.
GENERAL DESCRIPTION
The ADP195 is a high-side load switch designed for operation
between 1.1 V to 3.6 V and protected against reverse current
flow from output to input. This load switch provides power
domain isolation helping extended power domain isolation. The
device contains a low on-resistance, P-channel MOSFET that
supports over 1.1 A of continuous current and minimizes power
loss. The low 1 μA of quiescent current and ultralow shutdown
current make the ADP195 ideal for battery-operated portable
equipment. The built-in level shifter for enable logic makes the
ADP195 compatible with many processors and GPIO
controllers.
In addition to operating performance, the ADP195 occupies
minimal printed circuit board (PCB) space with an area of less
than 1.0 mm2 and a height of 0.60 mm.
It is available in an ultrasmall 1 mm × 1 mm, 4-ball, 0.5 mm
pitch WLCSP. A 6-lead 2 mm × 2 mm × 0.55 mm, 0.65 mm
pitch LFCSP is also available.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADP195
12
A VIN
VOUT
TOP VIEW
(Not to Scale)
B EN
GND
Figure 3. 4-Ball WLCSP Pin Configuration
VOUT1 1
VOUT2 2
GND 3
ADP195
TOP VIEW
(Not to Scale)
6 VIN1
5 VIN2
4 EN
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 4. 6-Lead LFCSP Pin Configuration
Table 4. WLCSP Pin Function Descriptions
Pin No.
Mnemonic Description
A1 VIN Input Voltage.
A2
VOUT
Output Voltage.
B1 EN Enable Input. Drive EN high to turn on the switch and drive EN low to turn off the switch.
B2
GND
Ground.
Table 5. LFCSP Pin Function Descriptions
Pin No.
Mnemonic Description
1
VOUT1
Output Voltage. Connect VOUT1 and VOUT2 together.
2
VOUT2
Output Voltage. Connect VOUT1 and VOUT2 together.
3
GND
Ground.
4 EN Enable Input. Drive EN high to turn on the switch and drive EN low to turn off the switch.
5
VIN2
Input Voltage. Connect VIN1 and VIN2 together.
6
VIN1
Input Voltage. Connect VIN1 and VIN2 together.
EP EP The exposed pad must be connected to ground.
Rev. C | Page 5 of 12
5 Page 
Data Sheet
TIMING
Turn-on delay is defined as the delta between the time that VEN
reaches >1.2 V until VOUT rises to ~10% of its final value. The
ADP195 includes circuitry to have typical 5 μs turn-on delay at
3.6 V VIN to limit the VIN inrush current. As shown in Figure 26,
the turn-on delay is dependent on the input voltage.
5.0
4.5
4.0
VVVVVEIIIINNNNN====
1.2V
1.8V
2.5V
3.6V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 5 10 15 20 25 30 35 40
TIME (µs)
Figure 26. Typical Turn-On Delay Time with Varying Input Voltage
The rise time is defined as the delta between the time from
10% to 90% of VOUT reaching its final value. It is dependent on
the RC time constant where C = load capacitance (CLOAD) and
R = RDSON||RLOAD. Because RDSON is usually smaller than RLOAD,
an adequate approximation for RC is RDSON × CLOAD. An input
or load capacitor is not needed for the ADP195; however, capacitors
can be used to suppress noise on the board. If significant load
capacitance is connected, inrush current is a concern.
VEN
1 VOUT
2
ADP195
VEN
1 VOUT
2
LOAD CURRENT
3
CH1 2V BW
CH2 1V
CH3 200mA Ω BW
M4µs
T 10%
A CH1 2.32V
Figure 28. Typical Rise Time and Inrush Current,
CLOAD = 1 μF, VIN = 1.8 V, Load = 200 mA
The turn-off time is defined as the delta between the time from
90% to 10% of VOUT reaching its final value. It is also dependent on
the RC time constant.
5.0
4.5
VVVEOONUUTT
AT
AT
200mA
100mA
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 20 40 60 80 100
TIME (µs)
Figure 29. Typical Turn-Off Time
LOAD CURRENT
3
CH1 2V BW
CH2 1V BW M4µs
CH3 200mA Ω BW
T 10%
A CH1 2.32V
Figure 27. Typical Rise Time and Inrush Current,
CLOAD = 1 μF, VIN = 1.8 V, No Load
Rev. C | Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADP195.PDF ] | |
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