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ADXRS450 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADXRS450
Beschreibung High Performance - Digital Output Gyroscope
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
ADXRS450 Datasheet, Funktion
Preliminary Technical Data
FEATURES
Complete rate gyroscope on a single chip
±300°/sec angular rate sensing
High vibration rejection over a wide frequency range
Excellent 25°/hr null offset stability
Internally temperature compensated
2000 g powered shock survivability
SPI digital output with 16-bit data-word
Low noise and low power
3.3 V and 5V operation
−40°C to +105°C operation
Ultra small, light, and RoHS compliant
Two package options
Low cost SOIC_CAV package for yaw rate (Z-axis) response
Innovative ceramic vertical mount package, which can be
oriented for pitch, roll, or yaw response
APPLICATIONS
Rotation sensing medical applications
Rotation sensing industrial and instrumentation
High performance platform stabilization
High Performance,www.DataSheet4U.com
Digital Output Gyroscope
ADXRS450
GENERAL DESCRIPTION
The ADXRS450 is an angular rate sensor (gyroscope) intended
for industrial, medical, instrumentation, stabilization, and other
high performance applications. An advanced, differential, quad
sensor design rejects the influence of linear acceleration, enabling
the ADXRS450 to operate in exceedingly harsh environments
where shock and vibration are present.
The ADXRS450 utilizes an internal, continuous self-test archi-
tecture. The integrity of the electromechanical system is checked
by applying a high frequency electrostatic force to the sense
structure to generate a rate signal that can be differentiated from
the baseband rate data and internally analyzed.
The ADXRS450 is capable of sensing angular rate of up to
±300°/sec. Angular rate data is presented as a 16-bit word, as
part of a 32-bit SPI message.
The ADXRS450 is available in a cavity plastic 16-lead SOIC
(SOIC_CAV) and an SMT-compatible vertical mount package
(LCC_V), and is capable of operating across both a wide voltage
range (3.3 V to 5 V) and temperature range (−40°C to +105°C).
CP5
VX
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATION
ADXRS450
Z-AXIS ANGULAR
RATE SENSOR
HV DRIVE
CLOCK
PHASE DIVIDER
LOCKED
LOOP AMPLITUDE
DETECT
BAND-PASS
FILTER
ADC 12
DEMOD
Q DAQ
P DAQ
Q FILTER
ST
CONTROL
ALU
DECIMATION
FILTER
TEMPERATURE
CALIBRATION
FAULT
DETECTION
EEPROM
Figure 1.
LDO
REGULATOR
PDD
DVDD
AVDD
SPI
INTERFACE
MOSI
MISO
SCLK
CS
DVSS
PSS
AVSS
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalog Devicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.






ADXRS450 Datasheet, Funktion
ADXRS450
Preliminary Technical Datawww.DataSheet4U.com
14 13 12 11 10 9
8
7 6 54 3 2 1
1 2 34 5 6 7
TOP VIEW
(Not to Scale)
Figure 4. LCC_V Pin Configuration
NC = NO
CONNECT
8 9 10 11 12 13 14
BACK VIEW
(Not to Scale)
Figure 5. LCC_V Pin Configuration, Horizontal Layout
Table 5. 14_Lead LCC_V Pin Function Descriptions
Pin No.
Mnemonic
Description
1 AVSS
2 AVDD
Analog Ground.
Analog Regulated Voltage. See Figure 22 for the applications circuit diagram.
3 MISO
Master In/Slave Out.
4 DVDD
Digital Regulated Voltage. See Figure 22 for the applications circuit diagram.
5 SCLK
SPI Clock.
6 CP5
High Voltage Supply. See Figure 22 for the applications circuit diagram.
7 RSVD
Reserved. This pin must be connected to DVSS.
8 RSVD
9 VX
Reserved. This pin must be connected to DVSS.
High Voltage Switching Node. See Figure 22 for the applications circuit diagram.
10 CS
Chip Select.
11 DVSS
12 MOSI
Digital Signal Ground.
Master Out/Slave In.
13 PSS
14 PDD
Switching Regulator Ground.
Supply Voltage.
Rev. PrA | Page 6 of 28

6 Page









ADXRS450 pdf, datenblatt
ADXRS450
SPI COMMUNICATION PROTOCOL
COMMAND/RESPONSE
Input/output is handled through a 32-bit, command/response
SPI interface. The command set and the format for the interface
is defined as follows:
Clock phase = clock polarity = 0
Additionally, the device response to the initial command is
0x00000001. This prevents the transmission of random data to
the master device upon the initial command/response exchange.
CS
Preliminary Technical Datawww.DataSheet4U.com
Table 7. SPI Signals
Signal
Serial Clock
Symbol
SCLK
Chip Select CS
Master Out
Slave In
MOSI
Master In
Slave Out
MISO
Description
Exactly 32 clock cycles during CS active
Active low
Data sent to the gyroscope device
from the main controller
Data sent to the main controller
from the gyroscope
SCLK
32 CLOCK
CYCLES
32 CLOCK
CYCLES
MOSI
COMMAND N
COMMAND N + 1
MISO
RESPONSE N – 1
Figure 24. SPI Protocol
RESPONSE N
Table 8. SPI Commands
Bit
Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sensor
Data
SQ1 SQ0 1 SQ2
CHK P
Read
1 0 0 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0
P
Write
0 1 0 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
Table 9. SPI Responses
Bit
Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sensor
Data
SQ2 SQ1 SQ0 P0 ST1 ST0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PLL Q NVM POR PWR CST CHK P1
Read
0 1 0 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P1
Write
0 0 1 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P1
R/W 0 0 0 P0 1 1 1 0 SM2 SM1 SM0 0 0 SPI RE DU
Error
PLL Q NVM POR PWR CST CHK P1
Rev. PrA | Page 12 of 28

12 Page





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