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PDF ADC141S626 Data sheet ( Hoja de datos )
| Número de pieza | ADC141S626 | |
| Descripción | Micro Power A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
November 30, 2007
ADC141S626
14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power
A/D Converter
General Description
The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling
Analog-to-Digital (A/D) converter. The converter is based on
a successive-approximation register architecture where the
differential nature of the analog inputs is maintained from the
internal track-and-hold circuits throughout the A/D converter
to provide excellent common-mode signal rejection. The
ADC141S626 features an external reference that can be var-
ied from 1.0V to VA and a zero-power track mode where the
ADC is consuming the minimum amount of supply current
while the internal sampling capacitor is tracking the applied
analog input voltage.
The serial data output is binary 2's complement and is com-
patible with several standards, such as SPI™, QSPI™, MI-
CROWIRE™, and many common DSP serial interfaces. The
conversion result is clocked out by the serial clock input and
is the result of the conversion currently in progress.
The ADC141S626 may be operated with independent analog
(VA) and digital input/output (VIO) supplies. VA and VIO can
range from 2.7V to 5.5V and can be set independent of each
other. This allows a user to maximize performance and min-
imize power consumption by operating the analog portion of
the ADC at a VA of 5V while communicating with a 3V con-
troller on the digital side. Operating from a single 3V supply,
the power consumption when operating at 200 kSPS is 2.0
mW. While operating from a single 5V supply, the power con-
sumption when operating at 250 kSPS is 4.8 mW. The power
consumption drops down to 4 µW and 13 µW respectively
when the ADC141S626 enters acquisition mode. The differ-
ential input, low power consumption, and small size make the
ADC141S626 ideal for direct connection to bridge sensors
and transducers in battery operated systems or remote data
acquisition applications.
Operation is guaranteed over the temperature range of −40°
C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The
ADC141S626 is available in a 10-lead MSOP package.
Features
■ True Differential Inputs
■ Guaranteed performance from 50 kSPS to 250 kSPS
■ External Reference
■ Zero-Power Track Mode
■ Wide Input Common-Mode Voltage Range
■ Operating Temperature Range of −40°C to +85°C
■ SPI™/QSPI™/MICROWIRE™/DSP compatible Serial
Interface
Key Specifications
■ Conversion Rate
■ INL
■ DNL
■ SNR
■ THD
■ ENOB
■ Power Consumption
■ — 200 kSPS, 3V
— 250 kSPS, 5V
— Power-Down, 3V
— Power-Down, 5V
50 kSPS to 250 kSPS
± 0.95 LSB (max)
± 0.95 LSB (max)
82 LSB (max)
− 90 dBc (typ)
13.3 bits (min)
2.0 mW (typ)
4.8 mW (typ)
4 µW (typ)
13 µW (typ)
Applications
■ Automotive Navigation
■ Portable Systems
■ Medical Instruments
■ Instrumentation and Control Systems
■ Motor Control
■ Direct Sensor Interface
Connection Diagram
TRI-STATE® is a trademark of National Semiconductor Corporation.
MICROWIRE™ is a trademark of National Semiconductor Corporation.
QSPI™ and SPI™ are trademarks of Motorola, Inc.
© 2007 National Semiconductor Corporation 300413
30041305
www.national.com
1 page  
Symbol
Parameter
Conditions
PWR
(Conv)
PWR
(PD)
Power Consumption, Conversion Mode
fSCLK = 3.6 MHz, fS = 200 kSPS, fIN = 20
kHz, VA = VIO = VREF = 3.0V
fSCLK = 4.5 MHz, fS = 250 kSPS, fIN = 20
kHz, VA = VIO = VREF = 5.0V
fSCLK = 0, VA = VIO = VREF = 3.0V
Power Consumption, Power Down Mode (Note 8)
(CS high)
fSCLK = 0, VA = VIO = VREF = 5.0V
(Note 8)
PSRR Power Supply Rejection Ratio
See the Specification Definitions for the
test condition
AC ELECTRICAL CHARACTERISTICS
fSCLK
fSCLK
fS
tACQ
tCONV
tAD
Maximum Clock Frequency
Minimum Clock Frequency
Maximum Sample Rate
Acquisition/Track Time
Conversion/Hold Time
Aperture Delay
VA = VIO = VREF = +2.7V to 5.5V
See the Specification Definitions
Typical
2.0
4.8
3
13
−85
4.8
6
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Limits
Units
3.0 mW
6.5 mW
4 µW (max)
17 µW (max)
dB
4.5 MHz (min)
0.9 MHz (max)
250 kSPS (min)
667 ns (min)
15 SCLK cycles
ns
ADC141S626 Timing Specifications (Note 7)
The following specifications apply for VA = VIO = VREF= +2.7V to 5.5V and fSCLK = 0.9 to 4.5 MHz, CL = 25 pF, Boldface limits
apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical Limits
Units
tCSS CS Setup Time prior to an SCLK rising edge
tDH DOUT Hold Time after an SCLK falling edge
tDA DOUT Access Time after an SCLK falling edge
tDIS
DOUT Disable Time after the rising edge of CS
(Note 11)
3
1/fSCLK - 3
10
28
6
1/fSCLK - 6
6
40
10 20
ns (min)
ns (max)
ns (min)
ns (max)
ns (max)
tCS Minimum CS Pulse Width
tEN DOUT Enable Time after the falling edge of CS
tCH SCLK High Time
tCL SCLK Low Time
tr DOUT Rise Time
tf DOUT Fall Time
5 20 ns (min)
32 51 ns (max)
67 89 ns (min)
67 89 ns (min)
7 ns
7 ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values
for maximum power dissipation listed above will be reached only when the ADC141S626 is operated in a severe fault condition (e.g. when input or output pins
are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.
Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 9: The value of VIO is independent of the value of VA. For example, VIO could be operating at 5V while VA is operating at 3V or VIO could be operating at 3V
while VA is operating at 5V.
Note 10: While the maximum sample rate is fSCLK/18, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/18.
Note 11: tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit.
5 www.national.com
5 Page 
Typical Performance Characteristics
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VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS,
TA = +25°C, and fIN = 20 kHz unless otherwise stated.
SINAD vs. TEMPERATURE
THD vs. TEMPERATURE
VA CURRENT vs. VA
30041372
30041371
VA CURRENT vs. SCLK FREQUENCY
30041335
VA CURRENT vs. TEMPERATURE
VREF CURRENT vs. VREF
30041355
30041354
11
30041334
www.national.com
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADC141S626.PDF ] | |
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