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ADP3206 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3206
Beschreibung 2-/3-/4-Phase Synchronous Buck Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP3206 Datasheet, Funktion
2-/3-/4-Phase Synchronous Buck
Controller for IMVP-5 CPUswww.DataSheet4U.com
ADP3206
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
6-bit digitally programmable 0.8375 V to 1.6 V output
±10 mV DAC accuracy over temperature
Logic-level PWM outputs for interface to
external high power drivers
Active current/thermal balancing between phases
Built-in power good/crowbar blanking supports
on-the-fly VID code changes
Programmable deep sleep offset and deeper sleep
reference voltage
Programmable soft transient control to minimize
inrush currents during output voltage changes
Programmable short circuit protection with
programmable latch-off delay
APPLICATIONS
Desk-note and notebook PC power supplies for IMVP-5
compliant Intel® processors
GENERAL DESCRIPTION
The ADP3206 is a highly efficient multiphase synchronous
buck-switching regulator controller optimized for converting
the notebook main supply into the core supply voltage required
by IMVP-5 Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between
0.8375 V and 1.6 V, and uses a multimode PWM architecture
to drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation.
The ADP3206 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3206 also provides accurate and reliable
short circuit protection, adjustable current limiting, deep sleep
and deeper sleep programming inputs, and a delayed power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
ADP3206 is specified over the commercial temperature range of
0°C to 100°C and is available in a 40-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
35
RAMPADJ RT
16 15
SD 13
UVLO
SHUTDOWN
AND BIAS
OSCILLATOR
GND 21
TTMASK 22
TTSENSE 23
VRTT 24
ADP3206
THERMAL
THROTTLING
CONTROL
CURRENT-
BALANCING
CIRCUIT
CSREF
CMP
SET EN
RESET
34 PWM1
CMP
CMP
RESET
33 PWM2
2-/3-/4-PHASE
DRIVER LOGIC
RESET
32 PWM3
CMP RESET
CROWBAR
31 PWM4
PWRGD 12
DELAY 14
ILIMIT 17
COMP 4
DELAY
SOFT
START
PRECISION
REFERENCE
CURRENT LIMIT
CURRENT-
LIMITING
CIRCUIT
28 SW1
27 SW2
26 SW3
25 SW4
19 CSSUM
18 CSREF
20 CSCOMP
VID
DAC
DEEP/
DEEPER
SLEEP
CONTROL
3 FB
11 DPSLP
10 DPSET
9 DPRSLP
8 DPRSET
5 PGMASK
29 OD2
30 OD1
6 STSET
2 7 40 39 38 37 36 1
FBRTN REF VID0 VID1 VID2 VID3 VID4 VID5
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






ADP3206 Datasheet, Funktion
ADP3206
TEST CIRCUITS
6-BIT CODE
+
1µF
5V
100nF
1k
4.7nF
250k
1 PIN 1
2 INDICATOR
3
4
5
ADP3206
6 TOP VIEW
7
8
9
10
30
29
28
27
26
25
24
23
22
21
1.25V
250k
20k
100nF
Figure 2. Closed-Loop Output Voltage Accuracy
5V
39k
1k
1.0V
ADP3206
VCC
35
CSCOMP
20
100nF
CSSUM
19
CSREF
18
+
GND
21
CSCOMP – 1V
VOS =
40
Figure 3. Current Sense Amplifier VOS
www.DataSheet4U.com
ADP3206
VCC
5V 35
10k
FB
3
COMP
4
200k
V
1.0V
200k
100nF
CSCOMP
20
CSSUM
19
CSREF
18
GND
21
+
VFB = FBV = 80mV – FBV = 0mV
Figure 4. Positioning Voltage
Rev. 0| Page 6 of 32

6 Page









ADP3206 pdf, datenblatt
ADP3206
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output in-
ductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor.
The gain of the amplifier is programmable by adjusting the
feedback resistor to set the load line required by the micro-
processor. The current information is then given as the
difference of CSREF CSCOMP. This difference signal is used
internally to offset the error amplifier for voltage positioning
and as a differential input for the current limit comparator.
To provide the best accuracy for current sensing, the CSA has
been designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can be
made extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output
current at the CSCOMP pin can be scaled to be equal to the
droop impedance of the regulator times the output current. This
droop voltage is then used to set the input control voltage to the
system. The droop voltage is subtracted from the error amplifier
offset voltage to tell the error amplifier where the output voltage
should be. This differs from previous implementations and
allows enhanced feed-forward response
CURRENT CONTROL MODE AND THERMAL
BALANCE
The ADP3206 has individual inputs for each phase which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system that has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for positioning
described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It is also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM ramp.
Detailed information about programming the ramp is given in
the applications section.
www.DataSheet4U.com
External resistors can be placed in series with individual phases
to create an intentional current imbalance if desired, such as
when one phase may have better cooling and can support
higher currents. Resistors RSW1 through RSW4 (see the typical
application circuit in Figure 1) can be used for adjusting
thermal balance. It is best to have the ability to add these
resistors during the initial design, so make sure placeholders are
provided in the layout.
To increase the current in any given phase, make RSW for that
phase larger (make RSW = 0 for the hottest phase and do not
change during balancing). Increasing RSW to only 500 makes
a substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
VOLTAGE CONTROL MODE
A high gain-bandwidth error amplifier is used for the voltage-
mode control loop. During normal mode, the noninverting
input voltage is set via the 6-bit VID logic code listed in Table 4,
while during Deeper Sleep operation, it is set to track the
buffered DPRSET voltage. The noninverting input voltage is
also offset by the droop voltage for offsetting the output voltage
as a function of current, commonly known as active voltage
positioning. The output of the amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor RB and is used for sensing and controlling the output
voltage at this point. During normal mode, a current source
from the FB pin flowing through RB is used for setting the no-
load offset voltage from the VID voltage. The no-load voltage is
negative with respect to the VID DAC. The main loop
compensation is incorporated in the feedback network between
FB and COMP.
Rev. 0| Page 12 of 32

12 Page





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