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PDF DS99R105 Data sheet ( Hoja de datos )
| Número de pieza | DS99R105 | |
| Descripción | (DS99R105 / DS99R106) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2007
www.DataSheet4U.com
DS99R105/DS99R106
3-40MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS99R105/DS99R106 Chipset translates a 24-bit paral-
lel bus into a fully transparent data/control LVDS serial stream
with embedded clock information. This single serial stream
simplifies transferring a 24-bit bus over PCB traces and cable
by eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size
and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on
the high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the serializer output edge rate for
the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
Features
■ 3 MHz–40 MHz clock embedded and DC-Balancing 24:1
and 1:24 data transmissions
■ Capable to drive shielded twisted-pair cable
■ User selectable clock edge for parallel data on both
Transmitter and Receiver
■ Internal DC Balancing encode/decode – Supports AC-
coupling interface with no external coding required
■ Individual power-down controls for both Transmitter and
Receiver
■ Embedded clock CDR (clock and data recovery) on
Receiver and no external source of reference clock
needed
■ All codes RDL (random data lock) to support live-
pluggable applications
■ LOCK output flag to ensure data integrity at Receiver side
■ Balanced TSETUP/THOLD between RCLK and RDATA on
Receiver side
■ PTO (progressive turn-on) LVCMOS outputs to reduce
EMI and minimize SSO effects
■ All LVCMOS inputs and control pins have internal
pulldown
■ On-chip filters for PLLs on Transmitter and Receiver
■ Integrated 100Ω input termination on Receiver
■ 4 mA Receiver output drive
■ 48-pin TQFP and 48-pin LLP packages
■ Pure CMOS .35 μm process
■ Power supply range 3.3V ± 10%
■ Temperature range 0°C to +70°C
■ 8 kV HBM ESD tolerance
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation 202081
20208101
www.national.com
1 page  
Symbol
tROS
tROH
tROS
tROH
tROS
tROH
tHZR
tLZR
tZHR
tZLR
tDD
Parameter
Conditions
ROUT (7:0) Setup Data to
RCLK (Group 1)
(Figure 15)
ROUT (7:0) Hold Data to RCLK
(Group 1)
ROUT (15:8) Setup Data to
RCLK (Group 2)
(Figure 15)
ROUT (15:8) Hold Data to
RCLK (Group 2)
ROUT (23:16) Setup Data to (Figure 15)
RCLK (Group 3)
ROUT (23:16) Hold Data to
RCLK (Group 3)
HIGH to TRI-STATE Delay
(Figure 13)
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
(Figure 12)
tDRDL
Deserializer PLL Lock Time
from Powerdown
RxIN_TOL_L Receiver INput TOLerance
Left
RxIN_TOL_R Receiver INput TOLerance
Right
(Figure 14)
(Notes 7, 8)
(Figure 16)
(Notes 6, 8, 10)
(Figure 16)
(Notes 6, 8, 10)
Pin/Freq.
ROUT [7:0]
ROUT [15:8],
LOCK
ROUT [23:16]
ROUT [23:0],
RCLK, LOCK
RCLK
3 MHz
40 MHz
3 MHz–40 MHz
3 MHz–40 MHz
Min Typ
Max Units
(0.40)*
tRCP
(0.40)*
tRCP
(0.40)*
tRCP
(0.40)*
tRCP
(0.40)*
tRCP
(0.40)*
tRCP
(29/56)*tRCP
(27/56)*tRCP
0.5*tRCP
0.5*tRCP
(27/56)*tRCP
(29/56)*tRCP
3
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ns
ns
ns
ns
ns
10 ns
3 10 ns
3 10 ns
3 10 ns
[4+(3/56)]T [4+(3/56)]T ns
+5.9
+18.5
5 50 ms
5 50 ms
0.25 UI
0.25 UI
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.
Note 8: Specification is guaranteed by characterization and is not tested in production.
Note 9: tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
Note 10: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 11: Figures 1, 2, 8, 12, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 12: Figures 5, 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 13: TxOUT_E_O is affected by pre-emphasis value.
5 www.national.com
5 Page 
www.DataSheet4U.com
FIGURE 15. Deserializer Setup and Hold Times
20208112
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
20208116
FIGURE 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
11 www.national.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet DS99R105.PDF ] | |
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