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DAC121S101Q Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DAC121S101Q
Beschreibung RRO Digital-to-Analog Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 20 Seiten
DAC121S101Q Datasheet, Funktion
DAC121S101/DAC121S101Q
February 19, 2010
www.DataSheet4U.com
12-Bit Micro Power, RRO Digital-to-Analog Converter
General Description
The DAC121S101 is a full-featured, general purpose 12-bit
voltage-output digital-to-analog converter (DAC) that can op-
erate from a single +2.7V to 5.5V supply and consumes just
177 µA of current at 3.6 Volts. The on-chip output amplifier
allows rail-to-rail output swing and the three wire serial inter-
face operates at clock rates up to 30 MHz over the specified
supply voltage range and is compatible with standard SPI,
QSPI, MICROWIRE and DSP interfaces. Competitive de-
vices are limited to 20 MHz clock rates at supply voltages in
the 2.7V to 3.6V range.
The supply voltage for the DAC121S101 serves as its voltage
reference, providing the widest possible output dynamic
range. A power-on reset circuit ensures that the DAC output
powers up to zero volts and remains there until there is a valid
write to the device. A power-down feature reduces power
consumption to less than a microWatt.
The low power consumption and small packages of the
DAC121S101 make it an excellent choice for use in battery
operated equipment.
The DAC121S101 is a direct replacement for the AD5320 and
the DAC7512 and is one of a family of pin compatible DACs,
including the 8-bit DAC081S101 and the 10-bit DAC101S101.
The DAC121S101 operates over the extended industrial tem-
perature range of −40°C to +105°C while the DAC121S101Q
operates over the Grade 1 automotive temperature range of
−40°C to +125°C. The DAC121S101 is available in a 6-lead
TSOT and an 8-lead MSOP and the DAC121S101Q is avail-
able in the 6-lead TSOT only.
Features
DAC121S101Q is AEC-Q100 Grade 1 qualified and is
manufactured on an Automotive Grade Flow.
Guaranteed Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to Zero Volts Output
Wide Temperature Range of −40°C to +125°C
Wide Power Supply Range of +2.7V to +5.5V
Small Packages
Power Down Feature
Key Specifications
Resolution
12 bits
DNL
+0.25, -0.15 LSB (typ)
Output Settling Time
8 µs (typ)
Zero Code Error
4 mV (typ)
Full-Scale Error
−0.06 %FS (typ)
Power Consumption
Normal Mode 0.64mW (3.6V) / 1.43mW (5.5V) typ
Pwr Down Mode 0.14µW (3.6V) / 0.39µW (5.5V) typ
Applications
Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Programmable Attenuators
Automotive
Pin Configuration
20114901
20114902
SPIis a trademark of Motorola, Inc.
© 2010 National Semiconductor Corporation
201149
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DAC121S101Q Datasheet, Funktion
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
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Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should be limited to 10
mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (TJMAX) for this device is 150°C. The maximum allowable power dissipation is dictated by TJMAX, the junction-
to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJMAX − TA) / θJA. The values for maximum
power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply
voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount
devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.
However, errors in the conversion result can occur if any input goes
−100mV input voltages 2.8VDC to ensure accurate conversions.
above
VA
or
below
GND
by
more
than
100
mV.
For
example,
if
VA
is
2.7VDC,
ensure
that
20114904
Note 8: To guarantee accuracy, it is required that VA be well bypassed.
Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB,
which is VREF / 4096 = VA / 4096.
DIGITAL FEEDTHROUGH is a measure of the energy inject-
ed into the analog output of the DAC from the digital inputs
when the DAC outputs are not updated. It is measured with a
full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual
output voltage with a full scale code (FFFh) loaded into the
DAC and the value of VA x 4095 / 4096.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Zero and Full-
Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE
is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog out-
put when the input code to the DAC register changes. It is
specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The end point method is used. INL for this product
is specified over a limited range, per the Electrical Tables.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-
est value or weight of all bits in a word. This value is
LSB = VREF / 2n
where VREF is the supply voltage for this product, and "n" is
the DAC resolution in bits, which is 12 for the DAC121S101.
MAXIMUM LOAD CAPACITANCE is the maximum capaci-
tance that can be driven by the DAC with output stability
maintained.
MONOTONICITY is the condition of being monotonic, where
the DAC has an output that never decreases when the input
code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest
value or weight of all bits in a word. Its value is 1/2 of VA.
POWER EFFICIENCY is the ratio of the output current to the
total supply current. The output current comes from the power
supply. The difference between the supply and output cur-
rents is the power consumed by the device without a load.
SETTLING TIME is the time for the output to settle to within
1/2 LSB of the final value after the input code is updated.
WAKE-UP TIME is the time for the output to settle to within
1/2 LSB of the final value after the device is commanded to
the active mode from any of the power down modes.
ZERO CODE ERROR is the output error, or voltage, present
at the DAC output after a code of 000h has been entered.
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DAC121S101Q pdf, datenblatt
Full-Scale Error vs. Clock Duty Cycle
Full-Scale Error vs. Temperature
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Supply Current vs. VA
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Supply Current vs. Temperature
5V Glitch Response
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Power-On Reset
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12
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12 Page





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