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PDF AD9941 Data sheet ( Hoja de datos )
| Número de pieza | AD9941 | |
| Descripción | 56 MSPS Imaging Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9941 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
Differential sensor input with 1 V p-p input range
0 dB/6 dB variable gain amplifier (VGA)
Low noise optical black clamp circuit
14-bit, 56 MSPS analog-to-digital converter (ADC)
No missing codes guaranteed
3-wire serial digital interface
3 V single-supply operation
Low power CMOS: 145 mW @ 3.0 V, 56 MHz
48-lead LQFP package
APPLICATIONS
Digital still cameras using CMOS imagers
Professional HDTV camcorders
Professional/high-end digital cameras
Broadcast cameras
Complete 14-Bit, 56 MSPS
Imaging Signal Processorwww.DataSheet4U.com
AD9941
GENERAL DESCRIPTION
The AD9941 is a complete analog signal processor for imaging
applications that do not require correlated double sampling
(CDS). It is also suitable for processing the output signal from
the AD9940 CDS front end product. It features a 56 MHz, single-
channel architecture designed to sample and condition the output
of CMOS imagers and CCD arrays already containing on-chip
CDS. The AD9941 signal chain consists of a differential input
sample-and-hold amplifier (SHA), a digitally controlled variable
gain amplifier (VGA), a black level clamp, and a 14-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface.
The AD9941 operates from a single 3 V supply, typically
dissipates 145 mW, and is packaged in a 48-lead LQFP.
VIN+
VIN–
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
REFT REFB
PBLK
AD9941
SHA
0dB, 6dB
VGA
BAND GAP
REFERENCE
14-BIT
ADC
CLP
14
INTERNAL
REGISTERS
8
DIGITAL
INTERFACE
BLK CLAMP
LEVEL
SL SCK SDATA
Figure 1.
ADCLK
DRVDD
DRVSS
DOUT
CLPOB
DVDD
DVSS
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
TIMING SPECIFICATIONS
CL = 20 pF, fADCLK = 56 MHz, refer to Figure 2 and Figure 8.
Table 4.
Parameter
SAMPLE CLOCKS
ADCLK Clock Period
ADCLK High/Low Pulse Width
CLPOB Pulse Width
Internal Clock Delay
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Rising Edge to SDATA Valid Hold
Symbol
TID
TOD
TH
fSCLK
tLS
tLH
tDS
tDH
AD9941
www.DataSheet4U.com
Min Typ Max
18
8
20
3
20
5
9
10
10
10
10
10
Unit
ns
ns
Pixels
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
TIMING DIAGRAMS
VIN–
N
N+1
N+2
N+8
N+9
VIN+
ADCLK
tID
tCONV
OUTPUT
DATA
tOD
N – 10
N–9
tH
N–8
N–1
NOTES
1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT ADCLK RISING EDGES (CAN BE INVERTED USING THE ADCPOL REGISTER).
2. INTERNAL SAMPLING DELAY (APERTURE) tID IS TYPICALLY 3ns.
3. OUTPUT DATA LATENCY IS NINE ADCLK CYCLES.
N
EFFECTIVE PIXELS
Figure 2. Input/Output Data Timing
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
IMAGER
SIGNAL
CLPOB
PBLK
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
NOTES
1. CLPOB OVERWRITES PBLK. PBLK DOES NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUPUT DATA IS ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE ADCLK CYCLES.
Figure 3. Typical Imager Timing
Rev. 0 | Page 5 of 16
EFFECTIVE DATA
5 Page 
Table 7. Serial Interface Registers
Address Data Bit Content Default Value
00 [0]
1
[2:1] 1
[3]
[4]
[5]
[6]
[7]
01 [5:0]
[6]
[7]
02 [7:0]
03 [7:0]
04 [7:0]
05 [0]
[1]
[7:2]
06 [7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
PARTSEL
OPERATION MODE
TESTMODE
ADCPOL
CLPMODE
TESTMODE
DOUT DISABLE
TESTMODE
CLPDISABLE
TESTMODE
TESTMODE
TESTMODE
TESTMODE
CLPLEVEL ENABLE
CLPUPDATE
TESTMODE
CLAMPLEVEL
AD9941
www.DataSheet4U.com
Description
1 = select AD9941, 0 = select AD9940
0 = standby mode
1 = 6 dB VGA gain mode
2 = test mode
3 = 0 dB VGA gain mode
Always set to 0
0 = ADCLK rising edge update
1 = ADCLK falling edge update
0 = fast clamp off
1 = fast clamp on (the OB loop time constant is reduced by half)
Always set to 0
0 = normal operation, 1 = data outputs are three-state
Always set to 0
0 = OB clamp enabled, 1= OB clamp disabled
Always set to 0
Always set to 72
Always set to 99
Always set to 16
0 = disable CLAMPLEVEL register, clamp level fixed at 492 LSB
1 = enable CLAMPLEVEL register, clamp level is set to value in
Register Value 06 CLAMPLEVEL
0 = ignore new value in CLAMPLEVEL register
1 = update new clamp level value with CLAMPLEVEL register
Always set to 0
OB clamp level (0 = 0 LSB, 123 = 492, 255 = 1020 LSB)
Clamp level (LSB) = 4 × REFBLK
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD9941.PDF ] | |
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