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PDF AD9940 Data sheet ( Hoja de datos )
| Número de pieza | AD9940 | |
| Descripción | Correlated Double Sampler | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Speed, Correlated Double Sampler
with Integrated Timing Driver
AD9940
FEATURES
56 MSPS correlated double sampler (CDS) with 6 dB gain
On-chip horizontal and RG timing driver
Single-supply operation (2.7 V min)
Precision Timing™ core with 0.37 ns resolution at 56 MSPS
Low power CMOS: 105 mW at 2.7 V (115 mW at 3.0 V)
48-lead LQFP and 48-lead LFCSP packages
APPLICATIONS
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
High speed data-acquisition systems
GENERAL DESCRIPTION
The AD9940 is a high speed, correlated double sampler for
high speed digital imaging applications. Integrated with a
programmable timing driver using the Precision Timing
core, the AD9940 features a 56 MHz CDS amplifier with
6 dB of fixed gain, an internal voltage reference supply,
and timing control for all the high speed clocks necessary
for CCD imaging systems. The Precision Timing core allows
adjustment of high speed clocks with a resolution of 0.37 ns.
Output buffers are also included, providing drive strength for
PCB traces and direct connection to an image signal processor
such as the AD9941.
The AD9940 is ideal for applications that need to place the
CDS and VGA/ADC circuits on separate PC boards. The fully
differential outputs of the AD9940 provide good signal integ-
rity when interfaced with the differential input AD9941. The
AD9940 operates from a single 2.7 V power supply, typically
dissipates 105 mW (excluding the H/RG drive current), and is
packaged in 48-lead LQFP and 48-lead LFCSP packages.
CCDIN
AD9940
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
VREF
CDS
BUF
DIFFN
DIFFP
RG
HL
H1 TO H4
HORIZONTAL
4 DRIVERS
.
INTERNAL
CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
HD SHP SHD
Figure 1.
CLI
SL SCK SDI
RST
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9940
Data Sheet
ANALOG SPECIFICATIONS
fCLI = 56 MHz, AVDD = OVDD = DVDD = TCVDD = 3.0 V, −25°C to +85°C, unless otherwise noted.
Table 2.
Parameter
CDS
Gain
Allowable CCD Reset Transient1
Maximum Input Range Before Saturation1
Maximum CCD Black Pixel Amplitude1
Peak Nonlinearity, 500 mV Input Signal
Power Supply Rejection (PSR)
ANALOG OUTPUTS2
Typical DIFFP Output Signal Range
Typical DIFFN Output Signal Range
Typical Common Mode Level
Maximum Differential Output Voltage Swing
Output Voltage Compliance
Maximum Load Capacitance
Minimum Load Resistance (if required)
1 Input signal characteristics are defined in Figure 2.
2 Output signal characteristics are defined in Figure 3.
Min Typ Max
5.0 5.5 6.0
500
1
±50
0.2
36
1.2
1.2
1.0
5,000
1.7
2
24
2.2
2.2
2.4
Unit Notes
dB
mV
V p-p
mV
% FS
dB
Measured with step change on supply
V 1.2 V corresponds to black level
V 2.2 V corresponds to black level
V Midscale voltage where DIFFP = DIFFN
V Defined as DIFFP − DIFFN
V Limitation of output swing into external load
pF Value for each output (AD9941 CIN is < 24 pF)
Ω Only use resistive loading if required by the
differential receiver. Proper dc biasing should
be used to be compatible with levels in Figure 3
500mV TYP
RESET TRANSIENT
50mV TYP
OPTICAL BLACK PIXEL
850mV TYP
INPUT SIGNAL RANGE
Figure 2. Input Signal Characteristics
1V MAX OUTPUT SIGNAL SWING, DIFFP AND DIFFN
2V p-p MAX DIFFERENTIAL SIGNAL, DIFFP–DIFFN
DIFFN
2.2V
BLACK
LEVEL
WHITE
LEVEL
1.7V
DIFFP
1.2V
GND
Figure 3. Output Signal Characteristics
Rev. A | Page 4 of 20
5 Page 
AD9940
Data Sheet
Address
7
8
9
10
11
12
13
Data Bit Content
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Default Value
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Name
HBLKTOG1_1 [0]
HBLKTOG1_1 [1]
HBLKTOG1_1 [2]
HBLKTOG1_1 [3]
HBLKTOG1_1 [4]
HBLKTOG1_1 [5]
HBLKTOG1_1 [6]
HBLKTOG1_1 [7]
HBLKTOG2_1 [8]
HBLKTOG2_1 [9]
HBLKTOG2_1 [10]
HBLKTOG2_1 [11]
TESTMODE
HBLKTOG2_1 [0]
HBLKTOG2_1 [1]
HBLKTOG2_1 [2]
HBLKTOG2_1 [3]
HBLKTOG2_1 [4]
HBLKTOG2_1 [5]
HBLKTOG2_1 [6]
HBLKTOG2_1 [7]
HBLKTOG1_2 [8]
HBLKTOG1_2 [9]
HBLKTOG1_2 [10]
HBLKTOG1_2 [11]
TESTMODE
HBLKTOG1_2 [0]
HBLKTOG1_2 [1]
HBLKTOG1_2 [2]
HBLKTOG1_2 [3]
HBLKTOG1_2 [4]
HBLKTOG1_2 [5]
HBLKTOG1_2 [6]
HBLKTOG1_2 [7]
HBLKTOG2_2 [8]
HBLKTOG2_2 [9]
HBLKTOG2_2 [10]
HBLKTOG2_2 [11]
TESTMODE
HBLKTOG2_2 [0]
HBLKTOG2_2 [1]
HBLKTOG2_2 [2]
HBLKTOG2_2 [3]
HBLKTOG2_2 [4]
HBLKTOG2_2 [5]
HBLKTOG2_2 [6]
HBLKTOG2_2 [7]
Description
HBLKTOG1 position for Sequence 1 (Bit 0)
HBLKTOG1 position for Sequence 1 (Bit 1)
HBLKTOG1 position for Sequence 1 (Bit 2)
HBLKTOG1 position for Sequence 1 (Bit 3)
HBLKTOG1 position for Sequence 1 (Bit 4)
HBLKTOG1 position for Sequence 1 (Bit 5)
HBLKTOG1 position for Sequence 1 (Bit 6)
HBLKTOG1 position for Sequence 1 (Bit 7)
HBLKTOG2 position for Sequence 1 (Bit 8)
HBLKTOG2 position for Sequence 1 (Bit 9)
HBLKTOG2 position for Sequence 1 (Bit 10)
HBLKTOG2 position for Sequence 1 (Bit 11)
Always set = 0
HBLKTOG2 position for Sequence 1 (Bit 0)
HBLKTOG2 position for Sequence 1 (Bit 1)
HBLKTOG2 position for Sequence 1 (Bit 2)
HBLKTOG2 position for Sequence 1 (Bit 3)
HBLKTOG2 position for Sequence 1 (Bit 4)
HBLKTOG2 position for Sequence 1 (Bit 5)
HBLKTOG2 position for Sequence 1 (Bit 6)
HBLKTOG2 position for Sequence 1 (Bit 7)
HBLKTOG1 position for Sequence 2 (Bit 8)
HBLKTOG1 position for Sequence 2 (Bit 9)
HBLKTOG1 position for Sequence 2 (Bit 10)
HBLKTOG1 position for Sequence 2 (Bit 11)
Always set = 0
HBLKTOG1 position for Sequence 2 (Bit 0)
HBLKTOG1 position for Sequence 2 (Bit 1)
HBLKTOG1 position for Sequence 2 (Bit 2)
HBLKTOG1 position for Sequence 2 (Bit 3)
HBLKTOG1 position for Sequence 2 (Bit 4)
HBLKTOG1 position for Sequence 2 (Bit 5)
HBLKTOG1 position for Sequence 2 (Bit 6)
HBLKTOG1 position for Sequence 2 (Bit 7)
HBLKTOG2 position for Sequence 2 (Bit 8)
HBLKTOG2 position for Sequence 2 (Bit 9)
HBLKTOG2 position for Sequence 2 (Bit 10)
HBLKTOG2 position for Sequence 2 (Bit 11)
Always set = 0
HBLKTOG2 position for Sequence 2 (Bit 0)
HBLKTOG2 position for Sequence 2 (Bit 1)
HBLKTOG2 position for Sequence 2 (Bit 2)
HBLKTOG2 position for Sequence 2 (Bit 3)
HBLKTOG2 position for Sequence 2 (Bit 4)
HBLKTOG2 position for Sequence 2 (Bit 5)
HBLKTOG2 position for Sequence 2 (Bit 6)
HBLKTOG2 position for Sequence 2 (Bit 7)
Rev. A | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD9940.PDF ] | |
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