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GTL2009 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer GTL2009
Beschreibung 3-bit GTL Front-Side Bus frequency comparator
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 17 Seiten
GTL2009 Datasheet, Funktion
GTL2009
www.DataSheet4U.com
3-bit GTL Front-Side Bus frequency comparator
Rev. 01 — 22 September 2005
Product data sheet
1. General description
The GTL2009 is designed for the Nocona and Dempsey/Blackford dual Intel Xeon
processor platforms to compare the Front-Side Bus (FSB) frequency settings and set the
common FSB frequency at the lowest setting if both processor slots are occupied or the
FSB setting of the occupied processor slot if only one processor is being used. A default
FSB frequency of 100 MHz is initially set upon power-up when VDD is greater than 1.5 V.
Magnitude comparisons and frequency multiplexing to compute the common FSB
frequency occurs when the two 3-bit FSB GTL inputs from the chip sets are valid. The
common FSB frequency GTL outputs switch from the default frequency to the computed
frequency when the GTL reference voltage input (VREF) crosses a static 0.6 V internally
generated input comparator reference voltage. The GTL2009 then continually monitors
the FSB frequency and slot occupied inputs for any further changes.
The Nocona and Dempsey/Blackford Xeon processors specify a VTT of 1.2 V and 1.1 V,
as well as a nominal Vref of 0.76 V and 0.73 V respectively. To allow for future voltage level
changes that may extend Vref to 0.63 of VTT (minimum of 0.693 V with VTT of 1.1 V) the
GTL2009 allows a minimum Vref of 0.66 V. Characterization results show that there is little
DC or AC performance variation between these levels.
The GTL2009 is a companion chip to the GTL2006 platform health management
GTL-to-LVTTL translator and the newer GTL2007 that adds an enable function that
disables the error output to the monitoring agent for platforms that monitor the individual
error conditions from each processor.
2. Features
s Compares FSB frequency inputs to set the lowest frequency as the common bus
frequency.
s Operates at a range of GTL signal levels
s 3.0 V to 3.6 V operation
s LVTTL I/O are not 5 V tolerant
s Companion chip to GTL2006 and GTL2007
s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
s Latch-up testing is done to JEDEC Standard JESD78, which exceeds 500 mA
s Available in TSSOP16 package






GTL2009 Datasheet, Funktion
Philips Semiconductors
GTL2009
www.DataSheet4U.com
3-bit GTL Front-Side Bus frequency comparator
8. Application design-in information
VTT
R
2R
56
VTT
common
front-side bus
VDD
VREF
BO3
BO2
BO1
AO2
AO1
VSS
1BI1
1BI2
1BI3
1AI
2AI
2BI1
2BI2
2BI3
Fig 3. Application diagram
PROCESSOR
A
slot A occupied
slot B occupied
PROCESSOR
B
002aaa998
8.1 Frequently asked questions
Question 1: When the GTL2009 is unpowered, the LVTTL inputs may be pulled up to
3.3 V and we want to make sure that there is no leakage path to the power rail under this
condition. Are the LVTTL inputs high-impedance when the device is unpowered and will
there be any leakage?
Answer 1: When the device is unpowered, the LVTTL inputs will be in a high-impedance
state and will not leak to VDD if they are pulled HIGH or LOW while the device is
unpowered.
Question 2: What is the condition of the GTL and LVTTL output pins when the device is
unpowered?
Answer 2: The open-drain GTL outputs will not leak to the power supply if they are pulled
HIGH or allowed to float while the device is unpowered. The GTL inputs will also not leak
to the power supply under the same conditions. The LVTTL totem pole outputs, however,
are not open-drain type outputs and there will be current flow on these pins if they are
pulled HIGH when VDD is at ground.
9397 750 13556
Product data sheet
Rev. 01 — 22 September 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
6 of 17

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GTL2009 pdf, datenblatt
Philips Semiconductors
GTL2009
www.DataSheet4U.com
3-bit GTL Front-Side Bus frequency comparator
14. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
y
Z
16
9
c
EA
X
HE v M A
pin 1 index
1
e
8
wM
bp
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
5.1
4.9
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT403-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13 0.1
0.40
0.06
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 12. Package outline SOT403-1 (TSSOP16)
9397 750 13556
Product data sheet
Rev. 01 — 22 September 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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