PDF ADC1610S Data sheet ( Hoja de datos )

Número de pieza	ADC1610S
Descripción	Single 16-bit ADC
Fabricantes	NXP Semiconductors
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No Preview Available ! ADC1610S series www.DataSheet4U.com Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 02 — 12 April 2010 Objective data sheet 1. General description The ADC1610S is a single-channel 16-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1610S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, because of a separate digital output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1610S is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 72.5 dBFS; SFDR, 88 dBc Sample rate up to 125 Msps 16-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Single 3 V supply Flexible input voltage range: 1 V to 2 V (peak-to-peak). CMOS or LVDS DDR digital outputs Power-down and Sleep modes Input bandwidth, 600 MHz Power dissipation, 430 mW at 80 Msps Serial Peripheral Interface (SPI) Duty cycle stabilizer Fast OuT of Range (OTR) detection INL ±1 LSB, DNL ±0.5 LSB Offset binary, two’s complement, gray code HVQFN40 package 3. Applications Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software define radio 1 page NXP Semiconductors ADC1610S series www.DataSheet4U.com ADC1610S series; CMOS or LVDS DDR digital output Table 3. Pin description (LVDS/DDR) digital outputs) Symbol Pin [1] Type [2] Description D14_D15_M 17 O differential output data D14 and D15 multiplexed, complement D14_D15_P 18 O differential output data D14 and D15 multiplexed, true D12_D13_M 19 O differential output data D12 and D13 multiplexed, complement D12_D13_P 20 O differential output data D12 and D13 multiplexed, true D10_D11_M 21 O differential output data D10 and D11multiplexed, complement D10_D11_P 22 O differential output data D10 and D11 multiplexed, true D8_D9_M 23 O differential output data D8 and D9 multiplexed, complement D8_D9_P 24 O differential output data D8 and D9 multiplexed, true D6_D7_M 25 O differential output data D6 and D7 multiplexed, complement D6_D7_P 26 O differential output data D6 and D7 multiplexed, true D4_D5_M 27 O differential output data D4 and D5 multiplexed, complement D4_D5_P 28 O differential output data D4 and D5 multiplexed, true D2_D3_M 29 O differential output data D2 and D3 multiplexed, complement D2_D3_P 30 O differential output data D2 and D3 multiplexed, true D0_D1_M 31 O differential output data D0 and D1 multiplexed, complement D0_D1_P 32 O differential output data D0 and D1 multiplexed, true DAVM 34 O data valid output clock, complement DAVP 35 O data valid output clock, true [1] Pins 1 to 16 and pins 36 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min VO output voltage pins D15 to D0; pins D15P to D0P; pins D15M to D0M −0.4 VDDA VDDO Tstg Tamb Tj analog supply voltage output supply voltage storage temperature ambient temperature junction temperature −0.4 −0.4 −55 −40 - Max +3.9 +3.9 +3.9 +125 +85 125 Unit V V V °C °C °C 8. Thermal characteristics Table 5. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions Typ [1] 22.5 [1] 11.7 [1] Value for six layers board in still air with a minimum of 25 thermal vias. Unit K/W K/W ADC1610S_SER_2 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 38 5 Page xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.2 Clock and digital output timing Table 8. Clock and digital output timing characteristics[1] Symbol Parameter Conditions ADC1610S065 Min Typ Max Clock timing input: pins CLKP and CLKM fclk tlat(data) clock frequency data latency time clock cycles 20 - - 65 14 - ADC1610S080 Min Typ Max 60 - 80 - 14 - δclk clock duty cycle DCS_EN = 1 30 50 70 30 50 DCS_EN = 0 45 50 55 45 50 td(s) sampling delay time - 0.8 - - 0.8 twake wake-up time - <tbd> - - <tbd> CMOS Mode Timing output: pins D15 to D0 and DAV tPD propagation delay DATA DAV - 3.9 - - 3.9 - 4.2 - - 4.2 tsu set-up time th hold time tr rise time[2] DATA DAV - 7.7 - - 6.5 - 6.7 - - 5.5 0.5 - 2.4 0.5 - 0.5 - 2.4 0.5 - tf fall time[2] DATA 0.5 - 2.4 0.5 - LVDS DDR mode timing output: pins D15P to D0P, D15M to D0M, DAVP and DAVM tPD propagation delay DATA DAV - 3.9 - - 3.9 - 4.2 - - 4.2 tsu set-up time th hold time tr rise time[3] DATA DAV - 5.1 - - - 2.0 - - 50 100 200 50 50 100 200 50 3.5 2.0 100 100 tf fall time[3] DATA DAV 50 100 200 50 50 100 200 50 100 100 70 55 - - - - - - 2.4 2.4 2.4 - - - - 200 200 200 200 ADC1610S105 Min Typ Max 75 - 105 - 14 - 30 50 70 45 50 55 - 0.8 - - <tbd> - - 3.9 - - 4.2 - - 4.7 - - 3.8 - 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 - 3.9 - - 4.2 - - 2.1 - - 2.0 - 50 100 200 50 100 200 50 100 200 50 100 200 ADC1610S125 Min Typ Max 100 - - 14 125 - 30 50 70 45 50 55 - 0.8 - - <tbd> - - 3.9 - - 4.2 - - 4.3 - - 3.5 - 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 - 3.9 - - 4.2 - - 1.4 - - 2.0 - 50 100 200 50 100 200 50 100 200 50 100 200 Unit MHz clock cycle % % ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps [1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. [2] Measured between 20 % to 80 % of VDDO. 11 Page

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