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ADC1413D Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer ADC1413D
Beschreibung Dual 14-bit ADC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 43 Seiten
ADC1413D Datasheet, Funktion
ADC1413D series
www.DataSheet4U.com
Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 04 — 23 April 2010
Preliminary data sheet
1. General description
The ADC1413D is a dual-channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1413D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V source
for analog and a 1.8 V source for the output driver, it embeds two serial outputs. Each lane
is differential and complies with the JESD204A standard. An integrated Serial Peripheral
Interface (SPI) allows the user to easily configure the ADC. A set of IC configurations is
also available via the binary level control pins taken, which are used at power-up. The
device also includes a SPI programmable full-scale to allow flexible input voltage range
from 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1413D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
„ SNR, 72 dBFS; SFDR, 86 dBc
„ Sample rate up to 125 Msps
„ Clock input divider by 2 for less jitter
contribution
„ 3 V, 1.8 V power supplies
„ Flexible input voltage range:
1 V to 2 V (peak-to-peak)
„ Two configurable serial outputs
„ INL ± 1 LSB; DNL ± 0.5 LSB
„ Pin compatible with the ADC1213D
series
„ HVQFN56 package
„ Input bandwidth, 600 MHz
„ Power dissipation, 995 mW at 80 Msps
„ SPI register programming
„ Duty cycle stabilizer
„ High IF capability
„ Offset binary, two’s complement, gray
code
„ Power-down mode and Sleep mode
„ Compliant with JESD204A serial
transmission standard
3. Applications
„ Wireless and wired broadband
communications
„ Spectral analysis
„ Ultrasound equipment
„ Portable instrumentation
„ Imaging systems
„ Software defined radio






ADC1413D Datasheet, Funktion
NXP Semiconductors
ADC1413D series
www.DataSheet4U.com
ADC1413D series; serial JESD204A interface
9. Static characteristics
Table 5. Characteristics
Symbol
Parameter
Conditions
Min Typ
Supplies
VDDA
VDDD
IDDA
IDDD
Ptot
P
analog supply voltage
digital supply voltage
analog supply current
digital supply current
total power dissipation
power dissipation
fclk = 125 Msps;
fi =70 MHz
fclk = 125 Msps;
fi = 70 MHz
fclk = 125 Msps
fclk = 105 Msps
fclk = 80 Msps
fclk = 65 Msps
power-down mode
2.85 3.0
1.65 1.8
- 343
- 150
- 1270
- 1150
- 995
- 885
- 30
standby mode
- 200
Digital inputs
Clock inputs: pins CLKP and CLKM, AC coupled
LVPECL
Vi(clk)dif
differential clock input
voltage
peak-to-peak
- ±0.8
LVDS
Vi(clk)dif
differential clock input
voltage
peak-to-peak
- ±0.4
SINE wave
Vi(clk)dif
differential clock input
voltage
peak-to-peak
±0.8 ±1.5
LVCMOS mode
VIL LOW-level input voltage
--
VIH HIGH-level input voltage
0.7VDDA
-
Logic inputs: Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, and SWING_1
VIL LOW-level input voltage
VIH HIGH-level input voltage
IIL LOW-level input current
IIH HIGH-level input current
SPI: pins CS, SDIO/DCS, and SCLK/DCS
-0
- 0.66VDDD
6 -
30 -
VIL LOW-level input voltage
VIH HIGH-level input voltage
IIL LOW-level input current
IIH HIGH-level input current
CI input capacitance
0
0.7VDDA
10
50
-
-
-
-
-
4
Max
3.4
1.95
-
-
-
-
-
-
-
-
-
-
-
0.3VDDA
-
-
-
+6
+30
0.3VDDA
VDDA
+10
+50
-
Unit
V
V
mA
mA
mW
mW
mW
mW
mW
mW
V
V
V
V
V
V
V
μA
μA
V
V
μA
μA
pF
ADC1413D_SER_4
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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ADC1413D pdf, datenblatt
NXP Semiconductors
ADC1413D series
www.DataSheet4U.com
ADC1413D series; serial JESD204A interface
11.1 Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
3.125 Gbps data rate
Tamb = 25 °C
DC coupling with two different receiver common-mode voltages
Fig 3. Eye diagram at 1 V receiver common-mode
005aaa088
Fig 4. Eye diagram at 2 V receiver common-mode
005aaa089
ADC1413D_SER_4
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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