PDF ADC1412D125 Data sheet ( Hoja de datos )

Número de pieza	ADC1412D125
Descripción	(ADC1412D065 - ADC1412D125) Dual 14-bit ADC
Fabricantes	NXP Semiconductors
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No Preview Available ! ADC1412D065/080/105/125www.DataSheet4U.com Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs Rev. 02 — 4 June 2009 Objective data sheet 1. General description The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1412D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily conﬁgure the ADC. The device also includes a programmable gain ampliﬁer with a ﬂexible input voltage range. With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D is ideal for use in communications, imaging and medical applications. 005aaa040 005aaa041 1.5 1.5 11 0.5 0.5 00 -0.5 -0.5 -1 -1 -1.5 0 4000 8000 12000 16000 -1.5 0 4000 8000 12000 16000 Fig 1. Integral Non-Linearity (INL) Fig 2. Differential Non-Linearity (DNL) 2. Features 0 dB -40 005aaa042 -80 -120 0 10 20 30 40 f (MHz) Fig 3. Output spectrum: −1 dBFS, 80 Msps, fi = 4.43 MHz I SNR, 73 dB I SFDR, 90 dBc I Sample rate up to 125 Msps I Dual-channel14-bit pipelined ADC core I Single 3 V supply I Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable ﬁne gain I CMOS or LVDS DDR digital outputs I INL ±1 LSB, DNL ±0.5 LSB (typical) I Input bandwidth, 650 MHz I Power dissipation, 775 mW at 80 Msps I SPI Interface I Duty cycle stabilizer I Fast OTR detection I Offset binary, 2’s complement, gray code I Power-down and Sleep modes I HVQFN64 package 1 page NXP Semiconductors ADC1412D065/080/105/125 www.DataSheet4U.com Dual 14-bit ADC 65, 80, 105 or 125 Msps ADC1412D065_080_105_125_2 Objective data sheet Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [1] Description VCMB 13 O common-mode output voltage; channel B AGND 14 G analog ground INBM 15 I complementary analog input; channel B INBP 16 I analog input; channel B VDDA 17 P analog power supply VDDA 18 P analog power supply SCLK/DFS 19 I SPI clock / data format select SDIO/ODS 20 I/O SPI data IO / output data standard CS 21 I SPI chip select CTRL 22 I control mode select DECB 23 O regulator decoupling node; channel B OTRB 24 O out of range; channel B DB13 25 O data output bit 13 (MSB); channel B DB12 26 O data output bit 12; channel B DB11 27 O data output bit 11; channel B DB10 28 O data output bit 10; channel B DB9 29 O data output bit 9; channel B DB8 30 O data output bit 8; channel B VDDO 31 P output power supply VDDO 32 P output power supply DB7 33 O data output bit 7; channel B DB6 34 O data output bit 6; channel B DB5 35 O data output bit 5; channel B DB4 36 O data output bit 4; channel B DB3 37 O data output bit 3; channel B DB2 38 O data output bit 2; channel B DB1 39 O data output bit 1; channel B DB0 40 O data output bit 0 (LSB); channel B n.c. 41 - - DAV 42 O data valid output clock DA0 43 O data output bit 0 (LSB); channel A DA1 44 O data output bit 1; channel A DA2 45 O data output bit 2; channel A DA3 46 O data output bit 3; channel A DA4 47 O data output bit 4; channel A DA5 48 O data output bit 5; channel A VDDO 49 P output power supply VDDO 50 P output power supply DA6 51 O data output bit 6; channel A DA7 52 O data output bit 7; channel A DA8 53 O data output bit 8; channel A DA9 54 O data output bit 9; channel A DA10 55 O data output bit 10; channel A DA11 56 O data output bit 11; channel A Rev. 02 — 4 June 2009 © NXP B.V. 2009. All rights reserved. 5 of 37 5 Page NXP Semiconductors ADC1412D065/080/105/125 www.DataSheet4U.com Dual 14-bit ADC 65, 80, 105 or 125 Msps 10. Dynamic characteristics 10.1 Dynamic Characteristics Table 7. Dynamic characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise speciﬁed. Symbol Parameter Conditions ADC1412D065 ADC1412D080 ADC1412D105 ADC1412D125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Analog signal processing α2H second fi = 3 MHz - 94 - - 94 - - 96 - - 96 - dBc harmonic level fi = 30 MHz - 93 - - 93 - - 92 - - 93 - dBc fi = 70 MHz - 90 - - 91 - - 91 - - 91 - dBc fi = 170 MHz - 88 - - 88 - - 85 - - 85 - dBc α3H third fi = 3 MHz - 92 - - 93 - - 91 - - 90 - dBc harmonic level fi = 30 MHz - 91 - - 92 - - 91 - - 89 - dBc fi = 70 MHz - 90 - - 90 - - 90 - - 87 - dBc fi = 170 MHz - 88 - - 87 - - 88 - - 87 - dBc THD total fi = 3 MHz - 88 - - 88 - - 87 - - 87 - dBc harmonic distortion fi = 30 MHz - 87 - - 87 - - 87 - - 86 - dBc fi = 70 MHz - 86 - - 86 - - 85 - - 84 - dBc fi = 170 MHz - 83 - - 83 - - 82 - - 82 - dBc ENOB effective fi = 3 MHz - 11.9 - - 11.9 - - 11.8 - - 11.8 - bits number of bits fi = 30 MHz - 11.7 - - 11.7 - - 11.7 - - 11.7 - bits fi = 70 MHz - 11.6 - - 11.6 - - 11.6 - - 11.6 - bits fi = 170 MHz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits SNR signal-to- fi = 3 MHz - 73.2 - - 73.1 - - 72.9 - - 72.5 - dBFS noise ratio fi = 30 MHz - 72.4 - - 72.3 - - 72.3 - - 72.2 - dBFS fi = 70 MHz - 71.8 - - 71.8 - - 71.7 - - 71.6 - dBFS fi = 170 MHz - 71.3 - - 71.2 - - 71.1 - - 71 - dBFS SFDR spurious- fi = 3 MHz - 91 - - 91 - - 90 - - 90 - dBc free dynamic fi = 30 MHz - 90 - - 90 - - 90 - - 89 - dBc range fi = 70 MHz - 89 - - 89 - - 88 - - 87 - dBc fi = 170 MHz - 86 - - 86 - - 85 - - 85 - dBc IMD Intermodul- fi = 3 MHz - 94 - - 94 - - 93 - - 93 - dBc ation distortion fi = 30 MHz - 93 - - 93 - - 93 - - 92 - dBc fi = 70 MHz - 92 - - 92 - - 91 - - 90 - dBc fi = 170 MHz - 89 - - 89 - - 88 - - 88 - dBc αct(ch) channel fi = 70 MHz - tbd - - tbd - - tbd - - tbd - dB crosstalk ADC1412D065_080_105_125_2 Objective data sheet Rev. 02 — 4 June 2009 © NXP B.V. 2009. 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