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ADC1215S Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer ADC1215S
Beschreibung Single 12-bit ADC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 39 Seiten
ADC1215S Datasheet, Funktion
ADC1215S series
www.DataSheet4U.com
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
with input buffer; CMOS or LVDS DDR digital outputs
Rev. 01 — 12 April 2010
Preliminary data sheet
1. General description
The ADC1215S is a single channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1215S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
thanks to a separate digital output supply.
The ADC1215S supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1215S is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures
that the input impedance remains constant and low and the performance consistent over
a wide frequency range.
2. Features and benefits
„ SNR, 70 dBFS / SFDR, 86 dBc
„ Input bandwidth, 600 MHz
„ Sample rate up to 125 Msps
„ Power dissipation, 635 mW at 80 Msps,
including analog input buffer
„ 12-bit pipelined ADC core
„ SPI
„ Clock input divider by 2 for less jitter „ Duty cycle stabilizer
contribution
„ Integrated input buffer
„ Fast OuT of Range (OTR) detection
„ Flexible input voltage range: 1 V (p-p) to „ INL ±1.25 LSB, DNL ±0.25 LSB
2 V (p-p)
„ CMOS or LVDS DDR digital outputs „ Offset binary, two’s complement, gray
code
„ Pin compatible with the ADC1415S
„ Power-down and Sleep modes
series, the ADC1015S series and the
ADC1115S125
„ HVQFN40 package






ADC1215S Datasheet, Funktion
NXP Semiconductors
ADC1215S series
www.DataSheet4U.com
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Table 3.
Symbol
n.c.
DAVM
DAVP
Pin description …continued (LVDS/DDR) digital outputs)
Pin [1] Type [2] Description
30 -
not connected
31 O data valid output clock, complement
32 O data valid output clock, true
[1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VO output voltage
pins D11 to D0 or
pins D11P to D0P
and D11M to D0M
0.4
VDDA(3V)
VDDA(5V)
VDDO
ΔVCC
Tstg
Tamb
Tj
analog supply voltage 3 V
analog supply voltage 5 V
output supply voltage
supply voltage difference
storage temperature
ambient temperature
junction temperature
on pin VDDA3V
on pin VDDA5V
VDDA(3V) VDDO
0.5
0.5
0.5
<tbd>
55
40
-
Max
+3.9
+4.6
+6.0
+4.6
<tbd>
+125
+85
125
Unit
V
V
V
V
V
°C
°C
°C
8. Thermal characteristics
Table 5. Thermal characteristics
Symbol
Rth(j-a)
Rth(j-c)
Parameter
thermal resistance from junction to ambient
thermal resistance from junction to case
Conditions
Typ
[1] 30.5
[1] 13.3
[1] Value for 6 layers board in still air with a minimum of 25 thermal vias.
Unit
K/W
K/W
ADC1215S_SER_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 April 2010
© NXP B.V. 2010. All rights reserved.
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10.2 Clock and digital output timing
Table 8. Clock and digital output timing characteristics[1]
Symbol
Parameter
Conditions
ADC1215S065
Min Typ Max
Clock timing input: pins CLKP and CLKM
fclk
tlat(data)
clock frequency
data latency
time
20 -
65
- 14 -
δclk clock duty cycle DCS_EN = 1 30 50 70
DCS_EN = 0 45 50 55
td(s) sampling delay
time
- 0.8 -
twake
wake-up time
-
CMOS mode timing output: pins D11 to D0 and DAV
<tbd> -
tPD
propagation
DATA
delay
DAV
- 3.9 -
- 4.2 -
tsu set-up time
- 7.7 -
th hold time
- 6.7 -
tr
rise time[2]
DATA
0.5 -
2.4
DAV
0.5 -
2.4
tf
fall time[2]
DATA
0.5 -
2.4
ADC1215S080
Min Typ Max
60 -
80
- 14 -
30 50 70
45 50 55
- 0.8 -
- <tbd> -
- 3.9 -
- 4.2 -
- 6.5 -
- 5.5 -
0.5 -
2.4
0.5 -
2.4
0.5 -
2.4
ADC1215S105
Min Typ Max
75 -
105
- 14 -
30 50 70
45 50 55
- 0.8 -
- <tbd> -
- 3.9 -
- 4.2 -
- 4.7 -
- 3.8 -
0.5 -
2.4
0.5 -
2.4
0.5 -
2.4
ADC1215S125
Min Typ Max
100 -
- 14
125
-
30 50 70
45 50 55
- 0.8 -
- <tbd> -
- 3.9 -
- 4.2 -
- 4.3 -
- 3.5 -
0.5 -
2.4
0.5 -
2.4
0.5 -
2.4
Unit
MHz
clocks
cycle
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns

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