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PDF ADC1213D Data sheet ( Hoja de datos )
| Número de pieza | ADC1213D | |
| Descripción | Dual 12-bit ADC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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ADC1213D series
www.DataSheet4U.com
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
Rev. 05 — 23 April 2010
Preliminary data sheet
1. General description
The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a SPI programmable full-scale to allow flexible input
voltage range from 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
SNR, 70 dBFS; SFDR, 86 dBc
Sample rate up to 125 Msps
Clock input divider by 2 for less jitter
contribution
3 V, 1.8 V single supplies
Flexible input voltage range:
1 V to 2 V (peak-to-peak)
Two configurable serial outputs
INL ± 1 LSB; DNL ± 0.5 LSB
Pin compatible with the ADC1213D
series
HVQFN56 package
Input bandwidth, 600 MHz
Power dissipation, 995 mW at 80 Msps
SPI register programming
Duty cycle stabilizer
High IF capability
Offset binary, two’s complement, gray
code
Power-down mode and Sleep mode
Compliant with JESD204A serial
transmission standard
3. Applications
Wireless and wired broadband
communications
Spectral analysis
Ultrasound equipment
Portable instrumentation
Imaging systems
Software defined radio
1 page  
NXP Semiconductors
ADC1213D series
www.DataShee
ADC1213D series
Table 2.
Symbol
AGND
VDDA
SENSE
VREF
VDDA
Pin description …continued
Pin Type [1]
52 G
53 P
54 I
55 I/O
56 P
Description
analog ground
analog power supply 3 V
reference programming pin
voltage reference input/output
analog power supply 3 V
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
[2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B
7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VDDA
VDDD
ΔVCC
Tstg
Tamb
Tj
analog supply voltage
digital supply voltage
supply voltage difference
storage temperature
ambient temperature
junction temperature
VDDA − VDDD
[1] −0.4
[2] −0.4
<tbd>
−55
−40
-
Max
+4.6
+2.5
<tbd>
+125
+85
125
Unit
V
V
V
°C
°C
°C
[1] The supply voltage VDDA may have any value between −0.5 V and +7.0 V provided that the supply voltage
differences ΔVCC are respected.
[2] The supply voltage VDDD may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ΔVCC are respected.
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Rth(j-c)
Thermal characteristics
Parameter
Conditions Typ
thermal resistance from junction to ambient
[1] 17.8
thermal resistance from junction to case
[1] 6.8
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
Unit
K/W
K/W
Table 5. Characteristics[1]
Symbol
Parameter
Supplies
VDDA
VDDD
IDDA
analog supply voltage
digital supply voltage
analog supply current
Conditions
fclk = 125 Msps;
fi =70 MHz
Min Typ Max Unit
2.85 3.0
3.4
V
1.65 1.8
1.95 V
- 343 -
mA
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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11. Clock and digital output timing
Table 7. Characteristics[1]
Symbol Parameter
Conditions
Clock timing input: pins CLKP and CLKM
fclk
tlat(data)
δclk
clock frequency
data latency time
clock duty cycle
clock cycles
DCS_EN = 1:
en
DCS_EN = 0:
dis
td(s)
twake
sampling delay time
wake-up time
ADC1213D065
Min Typ Max
20 -
307 -
30 50
65
850
70
45 50 55
- 0.8 -
- <tbd> -
ADC1213D080
Min Typ Max
60 -
250 -
30 50
80
283
70
45 50 55
- 0.8 -
- <tbd> -
ADC1213D105
Min Typ Max
75 -
190 -
30 50
105
226
70
45 50 55
- 0.8 -
- <tbd> -
ADC1213D125
Min Typ Max
100 -
160 -
30 50
125
170
70
45 50 55
- 0.8 -
- <tbd> -
Unit
Msps
ns
%
%
ns
ns
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V,
VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified.
11 Page | ||
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