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PDF ADC1207S080 Data sheet ( Hoja de datos )
| Número de pieza | ADC1207S080 | |
| Descripción | Single 12 bits ADC | |
| Fabricantes | NXP Semiconductors | |
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ADC1207S080
www.DataSheet4U.com
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF
sampling
Rev. 02 — 7 August 2008
Product data sheet
1. General description
The ADC1207S080 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct
Input Frequency (IF) sampling and supporting the most demanding use conditions in ultra
high IF radio transceivers for cellular infrastructure and other applications such as wireless
infrastructure, optical networking and fixed telecommunication. Due to its broadband input
capabilities, the ADC1207S080 is ideal for single and multiple carriers data conversion.
Operating at a maximum sampling rate of 80 MHz, analog input signals are converted into
12-bit binary coded digital words. All static digital inputs are CMOS compatible. All output
signals are Low-Voltage Complementary Metal-Oxide Semiconductor (LVCMOS)
compatible. The ADC1207S080 offers the most flexible acquisition control system
because of its programmable Complete Conversion Signal (CCS) that allows to adjust the
delay of the acquisition clock.
The ADC1207S080 offers the lowest input capacitance (< 1 pF) and therefore the highest
flexibility in front-end aliasing filter strategy because of its internal front-end buffer.
2. Features
I 12-bit resolution
I Differential input with 375 MHz bandwidth
I 90 dB SFDR; 71 dB S/N (fi = 225 MHz; fclk = 80 MHz; B = 5 MHz)
I 74 dB SFDR; 66.5 dB S/N (fi = 175 MHz; fclk = 80 MHz; B = Nyquist)
I High speed sampling rate up to 80 MHz
I Internal front-end buffer (input capacitance < 1 pF)
I Programmable acquisition output clock (complete conversion signal)
I Full-scale controllable from 1.5 V to 2 V (p-p); continuous scale
I Single 5 V power supply
I 3.3 V LVCMOS compatible digital outputs
I Binary or two’s-complement LVCMOS outputs
I CMOS compatible static digital inputs
I Only 2 clock cycles latency
I Industrial temperature range from −40 °C to +85 °C
I HTQFP48 package
1 page  
NXP Semiconductors
ADC1207S080
www.DataSheet4U.com
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VCCA
VCCD
VCCO
∆VCC
Vi(IN)
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
input voltage on pin IN
VCCA − VCCD
VCCD − VCCO
VCCA − VCCO
referenced to AGND
[1] −0.5
[1] −0.5
[2] −0.5
−1.0
−1.0
−1.0
0
Vi(INN)
input voltage on pin INN
referenced to AGND
0
Vi(CLK)
input voltage on pin CLK referenced to DGND
0
Vi(CLKN)
input voltage on pin CLKN referenced to DGND
0
IO
Tstg
Tamb
Tj
output current
storage temperature
ambient temperature
junction temperature
-
−55
−40
-
Max Unit
+7.0 V
+7.0 V
+5.0 V
+1.0 V
+4.0 V
+4.0 V
VCCA + 1
VCCA + 1
VCCD + 1
VCCD + 1
10
V
V
V
V
mA
+150
°C
+85 °C
150 °C
[1] The supply voltages VCCA and VCCD may have any value between −0.5 V and +7.0 V provided that the
supply voltage differences ∆VCC are respected.
[2] The supply voltage VCCO may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ∆VCC are respected.
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Rth(j-c)
Thermal characteristics
Parameter
Conditions Typ
thermal resistance from junction to ambient
[1] 36.2
thermal resistance from junction to case
[1] 14.3
[1] In compliance with JEDEC test board, in free air.
Unit
K/W
K/W
ADC1207S080_2
Product data sheet
Rev. 02 — 7 August 2008
© NXP B.V. 2008. All rights reserved.
5 of 21
5 Page 
NXP Semiconductors
ADC1207S080
www.DataSheet4U.com
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
0
power
spectrum
(dBc)
−40
−80
(1)
(2) (3)
(4)
014aaa435
(5) (6)
−120
−160
0
10 20
(1) fi 1H = 15 MHz; 0 dBc
(2) fi 2H = 5.1 MHz; −79.6 dBc
(3) fi 3H = 9.88 MHz; −82.1 dBc
(4) fi 4H = 20.1 MHz; −80.6 dBc
(5) fi 5H = 30 MHz; −74.7 dBc
(6) fi 6H = 35.1 MHz; −93.9 dBc
THD (5H): −72.2 dBc
SFDR: 74.7 dBc
Fig 4. Single tone; fi = 175 MHz; fCLK = 80 MHz
2.2
Vi(a)(p-p)
(V)
2.0
30 40
fi (MHz)
014aaa436
1.8
1.6
1.4
1.4 1.6 1.8 2.0 2.2
Vref(fs) (V)
Fig 5. ADC full-scale; Vi(a)(p-p) as a function of Vref(fs)
The ADC1207S080 allows modifying the ADC full-scale. This could be done with FSIN
(full-scale input) according to Figure 5.
ADC1207S080_2
Product data sheet
Rev. 02 — 7 August 2008
© NXP B.V. 2008. All rights reserved.
11 of 21
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