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ADC1206S070 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer ADC1206S070
Beschreibung (ADC1206S040 - ADC1206S070) Single 12 bits ADC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
ADC1206S070 Datasheet, Funktion
ADC1206S040/055/070
www.DataSheet4U.com
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Rev. 02 — 12 August 2008
Product data sheet
1. General description
The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters
(ADC) optimized for a wide range of applications such as cellular infrastructures,
professional telecommunications, imaging, and digital radio. It converts the analog input
signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All
static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS
compatible and all outputs are CMOS compatible. A sine wave clock input signal can also
be used.
2. Features
I 12-bit resolution
I Sampling rate up to 70 MHz
I 3 dB bandwidth of 245 MHz
I 5 V power supplies and 3.3 V output power supply
I Binary or twos complement CMOS outputs
I In-range CMOS compatible output
I TTL and CMOS compatible static digital inputs
I TTL and CMOS compatible digital outputs
I Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible
I Power dissipation 550 mW (typical)
I Low analog input capacitance (typical 2 pF), no buffer amplifier required
I Integrated sample and hold amplifier
I Differential analog input
I External amplitude range control
I Voltage controlled regulator included
I 40 °C to +85 °C ambient temperature
3. Applications
High-speed analog-to-digital conversion for:
I Cellular infrastructure
I Professional telecommunication
I Digital radio
I Radar
I Medical imaging
I Fixed network
I Cable modem






ADC1206S070 Datasheet, Funktion
NXP Semiconductors
ADC1206S040/055/070
www.DataSheet4U.com
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Vi(IN)
Vi(INN)
Vi(clk)(p-p)
input voltage on pin IN
input voltage on pin INN
peak-to-peak clock input
voltage
referenced to AGND
differential clock drive
at pins 35 and 36
0.3
0.3
-
IO
Tstg
Tamb
Tj
output current
storage temperature
ambient temperature
junction temperature
-
55
40
-
Max
VCCA
VCCA
VCCD
10
+150
+85
150
Unit
V
V
V
mA
°C
°C
°C
[1] The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that
the supply voltage differences VCC are respected.
9. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to ambient
Conditions
in free air
Typ Unit
75 K/W
10. Characteristics
Table 6. Characteristics
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 °C to 85 °C;
VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; Vref = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Test Min
[1]
Typ
Max Unit
Supplies
VCCA
VCCD
VCCO
ICCA
ICCD
ICCO
Ptot
analog supply
voltage
digital supply
voltage
output supply
voltage
analog supply
current
digital supply
current
output supply
current
total power
dissipation
I
I
fclk = 20 MHz; fi = 400 kHz
fclk = 40 MHz; fi = 4.43 MHz
fclk = 55 MHz; fi = 20 MHz
fclk = 55 MHz fi = 20 MHz
I
C
I
4.75
4.75
3.0
-
-
-
-
-
-
5.0
5.0
3.3
78
27
3
6.2
9.5
550
5.25 V
5.25 V
3.6 V
87 mA
30 mA
4 mA
9 mA
12 mA
660 mW
ADC1206S040_055_070_2
Product data sheet
Rev. 02 — 12 August 2008
© NXP B.V. 2008. All rights reserved.
6 of 32

6 Page









ADC1206S070 pdf, datenblatt
NXP Semiconductors
ADC1206S040/055/070
www.DataSheet4U.com
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 °C to 85 °C;
VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; Vref = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Test Min
[1]
Typ
Max Unit
Bit error rate (fclk = 55 MHz)
BER
bit error rate
fi = 20 MHz; VI = ±16 LSB at C
code 2047
Timing (CL = 10 pF)[9]
td(s) sampling delay
time
C
th(o) output hold
time
C
td(o) output delay
time
C
3-state output delay times; see Figure 4
tdZH float to active
HIGH delay
time
C
tdZL float to active
LOW delay
time
C
tdHZ active HIGH to
float delay time
C
tdLZ active LOW to
float delay time
C
-
-
4
-
-
-
-
-
1014
0.25
6.4
9.0
5.1
7.0
9.7
9.5
-
1
-
13
9.0
11
14
13
times/sample
ns
ns
ns
ns
ns
ns
ns
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p - p) and with a DC
level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal,
sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a
100 nF capacitor.
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case the CLKN pin has to be connected to the ground.
[3] The ADC input range can be adjusted with an external reference connected to Vref pin. This voltage has to be referenced to VCCA;
see Figure 12.
[4] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[5] Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
THD = 20 log
-(---α-----2---H-----)---2-----+------(---α-----3----H-----)---2-----+------((---αα-----41---HH-----))---22-----+------(---α-----5----H-----)---2-----+------(---α----6----H-----)---2-
where α1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.
[6] Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8.
ADC1206S040_055_070_2
Product data sheet
Rev. 02 — 12 August 2008
© NXP B.V. 2008. All rights reserved.
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