PDF ADC1206S055 Data sheet ( Hoja de datos )

Número de pieza	ADC1206S055
Descripción	(ADC1206S040 - ADC1206S070) Single 12 bits ADC
Fabricantes	NXP Semiconductors
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No Preview Available ! ADC1206S040/055/070 www.DataSheet4U.com Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Rev. 02 — 12 August 2008 Product data sheet 1. General description The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features I 12-bit resolution I Sampling rate up to 70 MHz I −3 dB bandwidth of 245 MHz I 5 V power supplies and 3.3 V output power supply I Binary or twos complement CMOS outputs I In-range CMOS compatible output I TTL and CMOS compatible static digital inputs I TTL and CMOS compatible digital outputs I Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible I Power dissipation 550 mW (typical) I Low analog input capacitance (typical 2 pF), no buffer ampliﬁer required I Integrated sample and hold ampliﬁer I Differential analog input I External amplitude range control I Voltage controlled regulator included I −40 °C to +85 °C ambient temperature 3. Applications High-speed analog-to-digital conversion for: I Cellular infrastructure I Professional telecommunication I Digital radio I Radar I Medical imaging I Fixed network I Cable modem 1 page NXP Semiconductors ADC1206S040/055/070 www.DataSheet4U.com Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 3. Symbol DGND2 OTC CE IR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCCO OGND CLKN CLK VCCD1 DGND1 SH AGND4 VCCA4 IN INN AGND1 Pin description …continued Pin Description 17 digital ground 2 18 control input twos complement output; active HIGH 19 chip enable input (CMOS level; active LOW) 20 in-range output 21 data output; bit 11 (Most Signiﬁcant Bit (MSB)) 22 data output; bit 10 23 data output; bit 9 24 data output; bit 8 25 data output; bit 7 26 data output; bit 6 27 data output; bit 5 28 data output; bit 4 29 data output; bit 3 30 data output; bit 2 31 data output; bit 1 32 data output; bit 0 (Least Signiﬁcant Bit (LSB)) 33 output supply voltage (3.3 V) 34 output ground 35 complementary clock input 36 clock input 37 digital supply voltage 1 (5 V) 38 digital ground 1 39 sample-and-hold enable input (CMOS level; active HIGH) 40 analog ground 4 41 analog supply voltage 4 (5 V) 42 analog input voltage 43 complementary analog input voltage 44 analog ground 1 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min VCCA VCCD VCCO ∆VCC analog supply voltage digital supply voltage output supply voltage supply voltage difference VCCA − VCCD VCCD − VCCO VCCA − VCCO [1] −0.3 [1] −0.3 [1] −0.3 −1.0 −1.0 −1.0 Max +7.0 +7.0 +7.0 +1.0 +4.0 +4.0 Unit V V V V V V ADC1206S040_055_070_2 Product data sheet Rev. 02 — 12 August 2008 © NXP B.V. 2008. All rights reserved. 5 of 32 5 Page NXP Semiconductors ADC1206S040/055/070 www.DataSheet4U.com Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise speciﬁed. Symbol Parameter Conditions Test Min [1] Typ Max Unit Spurious free dynamic range; see Figure 7, 13 and 14 SFDR spurious free dynamic range Effective number of bits[7] ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz C fi = 10 MHz C fi = 15 MHz C fi = 20 MHz C ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C fi = 10 MHz C fi = 15 MHz C fi = 20 MHz I ADC1206S070H; (fclk = 70 MHz) fi = 4.43 MHz C fi = 10 MHz C fi = 15 MHz C ENOB effective ADC1206S040H; (fclk = 40 MHz) number of bits fi = 4.43 MHz C fi = 10 MHz C fi = 15 MHz C fi = 20 MHz C ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C fi = 10 MHz C fi = 15 MHz C fi = 20 MHz I ADC1206S070H; (fclk = 70 MHz) fi = 4.43 MHz C fi = 10 MHz C fi = 15 MHz C Two-tone Intermodulation; (fclk = 55 MHz; fi = 20 MHz)[8] αIM intermodulation suppression C IMD3 third-order intermodulation distortion C - - - - - - - - - - - - - - - - - - - - - - - - 72 - 71 - 71 - 69 - 72 - 71 - 71 - 69 - 70 - 69 - 69 - 10.1 - 10.1 - 10.1 - 10 - 10.1 - 10.1 - 10 - 10 - 10 - 10 - 10 - −68 - −70 - dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS bits bits bits bits bits bits bits bits bits bits bits dB dB ADC1206S040_055_070_2 Product data sheet Rev. 02 — 12 August 2008 © NXP B.V. 2008. All rights reserved. 11 of 32 11 Page

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