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PDF ADC1113D125 Data sheet ( Hoja de datos )
| Número de pieza | ADC1113D125 | |
| Descripción | Dual 11-bit ADC | |
| Fabricantes | NXP Semiconductors | |
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ADC1113D125
www.DataSheet4U.com
Dual 11-bit ADC; serial JESD204A interface
Rev. 02 — 23 April 2010
Preliminary data sheet
1. General description
The ADC1113D125 is a dual-channel 11-bit Analog-to-Digital Converter (ADC) optimized
for high dynamic performances and low power at sample rates of 125 Msps. Pipelined
architecture and output error correction ensure the ADC1113D125 is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A format. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a SPI programmable full-scale to allow flexible input
voltage range from 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1113D125 ideal for use in communications, imaging,
and medical applications.
2. Features and benefits
SNR, 66.5 dBFS; SFDR, 86 dBc
Sample rate: 125 Msps
Clock input divider by 2 for less jitter
contribution
3 V, 1.8 V single supplies
Flexible input voltage range:
1 V to 2 V (peak-to-peak)
Two configurable serial outputs
INL ± 1.25 LSB; DNL ± 0.25 LSB
Pin compatible with the ADC1213D
series
HVQFN56 package
Input bandwidth, 600 MHz
Power dissipation, 1270 mW
SPI register programming
Duty cycle stabilizer
High IF capability
Offset binary, two’s complement, gray
code
Power-down mode and Sleep mode
Two JESD204A serial outputs
3. Applications
Wireless and wired broadband
communications
Spectral analysis
Ultrasound equipment
Portable instrumentation
Imaging systems
Software defined radio
1 page  
NXP Semiconductors
ADC1113D125
www.DataSheet4U.com
ADC1113D125; serial JESD204A interface
Table 2.
Symbol
SENSE
VREF
VDDA
Pin description …continued
Pin Type [1]
54 I
55 I/O
56 P
Description
reference programming pin
voltage reference input/output
analog power supply 3 V
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
[2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B.
7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VDDA
VDDD
ΔVCC
Tstg
Tamb
Tj
analog supply voltage
digital supply voltage
supply voltage difference
storage temperature
ambient temperature
junction temperature
VDDA − VDDD
[1] −0.4
[2] −0.4
<tbd>
−55
−40
-
Max
+4.6
+2.5
<tbd>
+125
+85
125
Unit
V
V
V
°C
°C
°C
[1] The supply voltage VDDA may have any value between −0.5 V and +7.0 V provided that the supply voltage
differences ΔVCC are respected.
[2] The supply voltage VDDD may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ΔVCC are respected.
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Rth(j-c)
Thermal characteristics
Parameter
Conditions Typ
thermal resistance from junction to ambient
[1] 17.8
thermal resistance from junction to case
[1] 6.8
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
Unit
K/W
K/W
ADC1113D125_2
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 41
5 Page 
NXP Semiconductors
ADC1113D125
www.DataSheet4U.com
ADC1113D125; serial JESD204A interface
11.1 Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 °C
• DC coupling with two different receiver common-mode voltages
Fig 3. Eye diagram at 1 V receiver common-mode
005aaa088
Fig 4. Eye diagram at 2 V receiver common-mode
005aaa089
ADC1113D125_2
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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