PDF ADC1006S055 Data sheet ( Hoja de datos )

Número de pieza	ADC1006S055
Descripción	(ADC1006S055 / ADC1006S070) Single 10 bits ADC
Fabricantes	NXP Semiconductors
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No Preview Available ! ADC1006S055/070 www.DataSheet4U.com Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 02 — 12 August 2008 Product data sheet 1. General description The ADC1006S055/070 are a family of Bipolar CMOS (BiCMOS) 10-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features I 10-bit resolution I Sampling rate up to 70 MHz I −3 dB bandwidth of 245 MHz I 5 V power supplies and 3.3 V output power supply I Binary or two’s complement CMOS outputs I In-range CMOS compatible output I TTL and CMOS compatible static digital inputs I TTL and CMOS compatible digital outputs I Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible I Power dissipation 550 mW (typical) I Low analog input capacitance (typical 2 pF), no buffer ampliﬁer required I Integrated sample-and-hold ampliﬁer I Differential analog input I External amplitude range control I Voltage controlled regulator included I −40 °C to +85 °C ambient temperature 3. Applications High-speed analog-to-digital conversion for: I Cellular infrastructure I Professional telecommunication I Digital radio I Radar I Medical imaging I Fixed network I Cable modem 1 page NXP Semiconductors ADC1006S055/070 www.DataSheet4U.com Single 10 bits ADC, up to 55 MHz or 70 MHz Table 3. Symbol OTC CE IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c. n.c. VCCO OGND CLKN CLK VCCD1 DGND1 SH AGND4 VCCA4 IN INN AGND1 Pin description …continued Pin Description 18 control input two’s complement output; active HIGH 19 chip enable input (CMOS level; active LOW) 20 in-range output 21 data output; bit 9 (Most Signiﬁcant Bit (MSB)) 22 data output; bit 8 23 data output; bit 7 24 data output; bit 6 25 data output; bit 5 26 data output; bit 4 27 data output; bit 3 28 data output; bit 2 29 data output; bit 1 30 data output; bit 0 (Least Signiﬁcant Bit (LSB)) 31 not connected 32 not connected 33 output supply voltage (3.3 V) 34 output ground 35 complementary clock input 36 clock input 37 digital supply voltage 1 (5 V) 38 digital ground 1 39 sample-and-hold enable input (CMOS level; active HIGH) 40 analog ground 4 41 analog supply voltage 4 (5 V) 42 analog input voltage 43 complementary analog input voltage 44 analog ground 1 8. Limiting values ADC1006S055_070_2 Product data sheet Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min VCCA VCCD VCCO ∆VCC Vi(IN) Vi(INN) analog supply voltage digital supply voltage output supply voltage supply voltage difference input voltage on pin IN input voltage on pin INN VCCA − VCCD VCCD − VCCO VCCA − VCCO referenced to AGND [1] −0.3 [1] −0.3 [1] −0.3 −1.0 −1.0 −1.0 0.3 0.3 Rev. 02 — 12 August 2008 Max +7.0 +7.0 +7.0 +1.0 +4.0 +4.0 VCCA VCCA Unit V V V V V V V V © NXP B.V. 2008. All rights reserved. 5 of 31 5 Page NXP Semiconductors ADC1006S055/070 www.DataSheet4U.com Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise speciﬁed. Symbol Parameter Conditions Test[1] Min Typ Max Unit Timing (CL = 10 pF)[9] td(s) sampling delay time th(o) output hold time td(o) output delay time 3-state output delay times; see Figure 4 C- C4 C- 0.25 1 6.4 - 9.0 13 ns ns ns tdZH ﬂoat to active HIGH delay time C- 5.1 9.0 ns tdZL ﬂoat to active LOW delay time C- 7.0 11 ns tdHZ active HIGH to ﬂoat delay time C- 9.7 14 ns tdLZ active LOW to ﬂoat delay time C- 9.5 13 ns [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. [2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC level vary 1 : 1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC level vary 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1 : 1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. [3] The ADC input range can be adjusted with an external reference connected to VREF pin. This voltage has to be referenced to VCCA; see Figure 12. [4] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. [5] Total Harmonic Distortion (THD) is obtained with the addition of the ﬁrst ﬁve harmonics: THD = 20 log (----α-----2---H-----)---2-----+------(---α-----3----H-----)---2-----+--(---a-(---α1----H-4---H-)--2--)---2-----+------(---α------)--2-----+------(---α-----6----H-----)---2- where α1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6. [6] Signal-to-noise ratio (S/N) takes into account all harmonics above ﬁve and noise up to Nyquist frequency; see Figure 8. [7] Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SIgnal-to_Noise_Distortion ratio (SINAD) is given by SINAD = ENOB × 6.02 + 1.76 dB; see Figure 5. [8] Intermodulation measured relative to either tone with analog input frequencies of 20 MHz and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. [9] Output data acquisition: the output data is available after the maximum delay of td(o); see Figure 3. ADC1006S055_070_2 Product data sheet Rev. 02 — 12 August 2008 © NXP B.V. 2008. All rights reserved. 11 of 31 11 Page

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