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ADC1003S040 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer ADC1003S040
Beschreibung (ADC1003S030 - ADC1003S050) Single 10 bits ADC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 20 Seiten
ADC1003S040 Datasheet, Funktion
ADC1003S030/040/050
www.DataSheet4U.com
Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with
voltage regulator
Rev. 02 — 7 August 2008
Product data sheet
1. General description
The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital
Converters (ADC) for professional video and other applications. They convert the analog
input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz.
All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible,
although a low-level sine wave clock input signal is allowed.
The device includes an internal voltage reference regulator. If the application requires that
the reference is driven via external sources the recommendation is to use one of the
ADC1004S030/040/050 family.
2. Features
I 10-bit resolution
I Sampling rate up to 50 MHz
I DC sampling allowed
I One clock cycle conversion only
I High signal-to-noise ratio over a large analog input frequency range
(9.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz)
I No missing codes guaranteed
I In-Range (IR) CMOS output
I Levels TTL and CMOS compatible digital inputs
I 3 V to 5 V CMOS digital outputs
I Low-level AC clock input signal allowed
I Internal reference voltage regulator
I Power dissipation only 235 mW (typical)
I Low analog input capacitance, no buffer amplifier required
I No sample-and-hold circuit required
3. Applications
High-speed analog-to-digital conversion for:
I Video data digitizing
I Radar
I Transient signal analysis
I Global Positioning System (GPS) receiver
I Σ∆ modulators






ADC1003S040 Datasheet, Funktion
NXP Semiconductors
ADC1003S030/040/050
www.DataSheet4U.com
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
10. Characteristics
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Supplies
VCCA
VCCD
VCCO
VCC
ICCA
ICCD
ICCO
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
analog supply current
digital supply current
output supply current
VCCA VCCD
VCCA VCCO
VCCA VCCO
fclk = 40 MHz;
ramp input
4.75 5.0
4.75 5.0
3.0 3.3
0.2 -
0.2 -
0.2 -
- 30
- 16
-1
5.25
5.25
5.25
+0.20
+2.25
+2.25
35
21
2
V
V
V
V
V
V
mA
mA
mA
Ptot
total power dissipation
fclk = 40 MHz;
ramp input
- 235 305 mW
Inputs
Clock input CLK (referenced to DGND)[1]
VIL LOW-level input voltage
VIH HIGH-level input voltage
IIL LOW-level input current Vclk = 0.8 V
IIH HIGH-level input current Vclk = 2 V
Zi input impedance
fclk = 40 MHz
Ci input capacitance
Inputs OE and TC (referenced to DGND)
0-
2-
1 0
-2
-2
-2
0.8
VCCD
+1
10
-
-
V
V
µA
µA
k
pF
VIL LOW-level input voltage
VIH HIGH-level input voltage
IIL LOW-level input current VIL = 0.8 V
IIH HIGH-level input current VIH = 2 V
VI (Analog input voltage referenced to AGND)
0-
2-
1 -
--
0.8
VCCD
-
1
V
V
µA
µA
IIL LOW-level input current VI = VRB = 1.3 V
- 0-
IIH HIGH-level input current VI = VRT = 3.67 V
- 35 -
Zi input impedance
fi = 4.43 MHz
- 8-
Ci input capacitance
- 5-
Reference voltages for the resistor ladder using the internal voltage regulator see Table 7
µA
µA
k
pF
VRB
VRT
Vref(dif)
voltage on pin RB
voltage on pin RT
differential reference
voltage
VRT VRB
1.1 1.3
3.4 3.6
2.25 2.3
1.5 V
3.8 V
2.35 V
Iref reference current
- 9.39 - mA
ADC1003S030_040_050_2
Product data sheet
Rev. 02 — 7 August 2008
© NXP B.V. 2008. All rights reserved.
6 of 20

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ADC1003S040 pdf, datenblatt
NXP Semiconductors
ADC1003S030/040/050
www.DataSheet4U.com
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
VCCD
OE
50 %
output
data
output
data
LOW
HIGH
tdLZ
tdZL
HIGH
10 %
50 %
tdHZ
tdZH
90 %
LOW
50 %
ADC1003S050
OE
3.3 k
15 pF
VCCD
S1
TEST
tdLZ
tdZL
tdHZ
tdZH
S1
VCCD
VCCD
DGND
DGND
014aaa334
frequency on pin OE = 100 kHz
Fig 5. Timing diagram and test conditions of 3-state output delay time.
code 1023
VI
code 0
ts(LH)
50%
2 ns
ts(HL)
50%
2 ns
CLK
50%
0.5 ns
Fig 6. Analog input settling-time diagram
50%
0.5 ns
014aaa327
ADC1003S030_040_050_2
Product data sheet
Rev. 02 — 7 August 2008
© NXP B.V. 2008. All rights reserved.
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