Datenblatt-pdf.com


ADC0808S250 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer ADC0808S250
Beschreibung (ADC0808S125 / ADC0808S250) Single 8-bit ADC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 23 Seiten
ADC0808S250 Datasheet, Funktion
ADC0808S125/250
www.DataSheet4U.com
Single 8-bit ADC, up to 125 MHz or 250 MHz
Rev. 03 — 24 February 2009
Product data sheet
1. General description
The ADC0808S is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC)
optimized for telecommunication transmission control systems and tape drive
applications. It allows signal sampling frequencies up to 250 MHz.
The ADC0808S clock inputs are selectable between 1.8 V Complementary Metal Oxide
Semiconductor (CMOS) or Low-Voltage Differential Signals (LVDS). The data output
signal levels are 1.8 V CMOS.
All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and DEL1) are 1.8 V
CMOS compatible.
The ADC0808S offers the most flexible acquisition control system possible due to its
programmable Complete Conversion Signal (CCS) which allows the delay time of the
acquisition clock and acquisition clock frequency to be adjusted.
The ADC0808S is supplied in an HTQFP48 package.
2. Features
I 8-bit resolution
I High-speed sampling rate up to 250 MHz
I Maximum analog input frequency up to 560 MHz
I Programmable acquisition output clock (complete conversion signal)
I Differential analog input
I Integrated voltage regulator or external control for analog input full-scale
I Integrated voltage regulator for input common-mode reference
I Selectable 1.8 V CMOS or LVDS clock input
I 1.8 V CMOS digital outputs
I 1.8 V CMOS compatible static digital inputs
I Binary or 2’s complement CMOS outputs
I Only 2 clock cycles latency
I Industrial temperature range from 40 °C to +85 °C
I HTQFP48 package
3. Applications
I 2.5G and 3G cellular base infrastructure radio transceivers
I Wireless access systems
I Fixed telecommunications






ADC0808S250 Datasheet, Funktion
NXP Semiconductors
ADC0808S125/250
www.DataSheet4U.com
Single 8-bit ADC, up to 125 MHz or 250 MHz
Table 4. Clock input format selection
Pin CLKSEL
HIGH or not connected
LOW
Clock input signal
Pins CLK+ and CLK
LVDS
1.8 V CMOS
7.2 Digital output coding
The digital outputs are 1.8 V CMOS compatible.
The data output format can be either binary or 2’s complement.
Table 5. Output coding with differential inputs
Vi(p-p) = 2.0 V; Vref(fs) = 1.25 V; typical values to AGND.
Code
Inputs (V)
Output
Underflow
Vi(IN)
< 0.45
Vi(INN)
> 1.45
Pin IR
LOW
0 0.45 1.45
HIGH
1 --
HIGH
: ::
:
127 0.95 0.95
HIGH
: ::
:
254 -
-
HIGH
255 1.45 0.45
HIGH
Overflow > 1.45
< 0.45
LOW
Outputs D7 to D0
Binary
2’s complement
0000 0000 1000 0000
0000 0000 1000 0000
0000 0001 1000 0001
::
0111 1111 1111 1111
::
1111 1110 0111 1110
1111 1111 0111 1111
1111 1111 0111 1111
The in-range CMOS output pin IR will be HIGH during normal operation. When the ADC
input reaches either positive or negative full-scale, the IR output will be LOW.
Selection between output coding is controlled by pins OTC and CE_N.
Table 6. Output format selection
2’s complement outputs Chip enable
Pin OTC
Pin CE_N
LOW
LOW
HIGH
LOW
X [1] HIGH
Output data
Pins D0 to D7, CCS and IR
active; binary
active; 2’s complement
high-impedance
[1] X = don’t care.
ADC0808S125_ADC0808S250_3
Product data sheet
Rev. 03 — 24 February 2009
© NXP B.V. 2009. All rights reserved.
6 of 23

6 Page









ADC0808S250 pdf, datenblatt
NXP Semiconductors
ADC0808S125/250
www.DataSheet4U.com
Single 8-bit ADC, up to 125 MHz or 250 MHz
11. Dynamic characteristics
Table 13. Dynamic characteristics
VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;
Tamb = 40 °C to +85 °C; Vi(IN) Vi(INN) = 2.0 V 0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at
VCCA = 3.3 V, VCCD = VCCO = 1.8 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Clock timing input: pins CLK+ and CLK
fclk(min)
minimum clock frequency
fclk(max) maximum clock frequency
tw(clk)
clock pulse width
fclk = 125 MHz
Timing output: pins D0 to D7 and IR[1]; see Figure 5
--
250 -
1.8 -
1 MHz
- MHz
- ns
td(s) sampling delay time
1.8 V CMOS clock
LVDS clock
- 1.3 - ns
- 1.65 - ns
th(o) output hold time
1.8 V CMOS clock
LVDS clock
3.3 4.4 -
4.2 4.8 -
ns
ns
td(o) output delay time
1.8 V CMOS clock
LVDS clock
- 5.4 6.9 ns
- 5.8 7.3 ns
Timing complete conversion signal: pin CCS; see Figure 6
fCCS(max)
td(CCS)
maximum CCS frequency
CCS delay time
DEL0 = HIGH; DEL1 = LOW
DEL0 = LOW; DEL1 = HIGH
125 -
- 0.3
- 0.8
-
-
-
MHz
ns
ns
DEL0 = HIGH; DEL1 = HIGH
- 1.9 - ns
3-state output delay time: pins CCS, IR and D7 to D0
tdZH float to active HIGH delay time
tdZL float to active LOW delay time
tdHZ active HIGH to float delay time
tdLZ active LOW to float delay time
Analog signal processing (50 % clock duty factor); see Section 12
- 2.1 - ns
- 2.2 - ns
- 3.3 - ns
- 2.9 - ns
INL
DNL
integral non-linearity
differential non-linearity
fclk = 20 MHz; fi = 21.4 MHz
- ±0.82 - LSB
fclk = 20 MHz; fi = 21.4 MHz; no - ±0.4 - LSB
missing code guaranteed
EO offset error
EG gain error
B bandwidth
VCCA = 3.3 V; VCCD = 1.8 V;
Tamb = 25 °C; output code = 127
spread from device to device;
VCCA = 3.3 V; VCCD = 1.8 V;
Tamb = 25 °C
fclk = 125 MHz; 3 dB; full-scale
input
-
-
[2] -
2.5 -
1.85 -
560 -
mV
%
MHz
THD
total harmonic distortion
Nth(RMS)
S/N
RMS thermal noise
signal-to-noise ratio
fclk = 125 MHz; fi = 78 MHz
fclk = 250 MHz; fi = 125 MHz
shorted input; fclk = 125 MHz
fclk = 125 MHz; fi = 78 MHz
fclk = 250 MHz; fi = 125 MHz
[3] -
-
-
[4] -
-
53 -
53 -
0.5 -
48 -
47 -
dB
dB
LSB
dBc
dBc
ADC0808S125_ADC0808S250_3
Product data sheet
Rev. 03 — 24 February 2009
© NXP B.V. 2009. All rights reserved.
12 of 23

12 Page





SeitenGesamt 23 Seiten
PDF Download[ ADC0808S250 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADC0808S250(ADC0808S125 / ADC0808S250) Single 8-bit ADCNXP Semiconductors
NXP Semiconductors

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche