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ADC0804S030 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer ADC0804S030
Beschreibung (ADC0804S030 - ADC0804S050) Single 8 bits ADC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 19 Seiten
ADC0804S030 Datasheet, Funktion
ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Rev. 02 — 14 August 2008
Product data sheet
1. General description
The ADC0806030/040/050 are a family of 8-bit high-speed, low-power Analog-to-Digital
Converters (ADC) for professional video and other applications. It converts the analog
input signal into 8-bit binary coded digital signals at a maximum sampling rate of 50 MHz.
All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible,
although a low-level sine wave clock input signal can also be used.
The device requires an external source to drive its reference ladder. If the application
requires that the reference is driven via internal sources, NXP recommends you use one
of the ADC1003S030/040/050 family.
2. Features
I 8-bit resolution
I Sampling rate up to 50 MHz
I DC sampling allowed
I One clock cycle conversion only
I High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits
at 4.43 MHz full-scale input at fclk = 40 MHz)
I No missing codes guaranteed
I In-Range (IR) CMOS output
I TTL and CMOS levels compatible digital inputs
I 3 V to 5 V CMOS digital outputs
I Low-level AC clock input signal allowed
I External reference voltage regulator
I Power dissipation only 175 mW (typical)
I Low analog input capacitance, no buffer amplifier required
I No sample-and-hold circuit required
3. Applications
I Video data digitizing
I Radar
I Transient signal analysis
I Σ∆ modulators
I Medical imaging
I Barcode scanner
I Global Positioning System (GPS) receiver






ADC0804S030 Datasheet, Funktion
NXP Semiconductors
ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
10. Characteristics
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Supplies
VCCA
VCCD
VCCO
VCC
ICCA
ICCD
ICCO
Ptot
Inputs
analog supply voltage
digital supply voltage
output supply voltage
supply voltage
difference
analog supply current
digital supply current
output supply current
total power dissipation
VCCA VCCD
VCCA VCCO
VCCD VCCO
fclk = 40 MHz; ramp input
fclk = 40 MHz; ramp input
4.75
4.75
3.0
0.20
0.20
0.20
-
-
-
-
5.0 5.25 V
5.0 5.25 V
3.3 5.25 V
-
+0.20
V
-
+2.25
V
-
+2.25
V
18 24
mA
16 21
mA
12
mA
175 247
mW
Clock input CLK (referenced to DGND)[1]
VIL LOW-level input voltage
VIH HIGH-level input
voltage
0 - 0.8 V
2
-
VCCD
V
IIL LOW-level input current Vclk = 0.8 V
IIH HIGH-level input current Vclk = 2 V
Zi
input impedance
fclk = 40 MHz
Ci input capacitance
OE and TC (referenced to DGND); see Table 8
1 - +1 µA
- 2 10 µA
-
2-
k
-
2-
pF
VIL LOW-level input voltage
VIH HIGH-level input
voltage
0 - 0.8 V
2
-
VCCD
V
IIL LOW-level input current VIL = 0.8 V
IIH HIGH-level input current VIH = 2.0 V
VI (analog input voltage referenced to AGND)
1
--
µA
-
-1
µA
IIL LOW-level input current VI = VRB = 1.3 V
IIH HIGH-level input current VI = VRT = 3.67 V
Zi
input impedance
fi = 4.43 MHz
Ci input capacitance
Reference voltages for the resistor ladder; see Table 7
-
0-
µA
-
35 -
µA
-
8-
k
-
5-
pF
VRB voltage on pin RB
VRT voltage on pin RT
1.2 1.3 2.45 V
3.2
3.67
VCCA 0.8 V
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
6 of 19

6 Page









ADC0804S030 pdf, datenblatt
NXP Semiconductors
ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
VCCD
OE
50 %
output
data
output
data
LOW
HIGH
tdLZ
tdZL
HIGH
10 %
50 %
tdHZ
tdZH
90 %
LOW
50 %
ADC0804S030
OE
3.3 k
15 pF
VCCD
S1
TEST
tdLZ
tdZL
tdHZ
tdZH
S1
VCCD
VCCD
DGND
DGND
014aaa552
frequency on pin OE = 100 kHz
Fig 5. Timing diagram and test conditions of 3-state output delay time
code 255
VI
code 0
ts(LH)
50 %
2 ns
ts(HL)
50 %
2 ns
CLK
50 %
0.5 ns
Fig 6. Analog input settling time diagram
50 %
0.5 ns
014aaa400
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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