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AD7643 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7643
Beschreibung 1.25 MSPS PulSAR ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD7643 Datasheet, Funktion
18-Bit, 1.25 MSPS PulSAR ADC®www.DataSheet4U.com
AD7643
FEATURES
Throughput: 1.25 MSPS
INL: ±1.5 LSB typical, ±3 LSB maximum (±11 ppm of full scale)
18-bit resolution with no missing codes
Dynamic range: 95 dB typical
SINAD: 93.5 dB typical @ 20 kHz (VREF = 2.5 V)
THD: −113 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typical drift 8 ppm/°C; TEMP output
Differential input range: ±VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation
65 mW typical @ 1.25 MSPS with internal REF
2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with the AD7641 and other PulSAR ADC’s
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
GENERAL DESCRIPTION
The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution
SAR, fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. The part has no
latency and can be used in asynchronous rate applications. The
AD7643 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7643 is only available in Pb-free packages with
operation specified from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
REF
REF AMP
SWITCHED
CAP DAC
AD7643
SERIAL
PORT 18
PARALLEL
INTERFACE
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OVDD
OGND
D[17:0]
MODE0
MODE1
BUSY
RD
CS
D0/OB/2C
CNVST
Figure 1.
Table 1. PulSAR 48-Lead Selection
Type/kSPS
100 to
250
500 to
570
Pseudo
Differential
AD7651,
AD7660,
AD7661
AD7650,
AD7652,
AD7664,
AD7666
True Bipolar
AD7610, AD7665
AD7663
True
Differential
AD7675 AD7676
18-Bit
Multichannel/
Simultaneous
AD7631,
AD7678
AD7679
AD7654
650 to
1000
AD7653,
AD7667
AD7612,
AD7671
AD7677
AD7634,
AD7674
AD7655
>1000
AD7621,
AD7622,
AD7623
AD7641,
AD7643
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7643 is a 1.25 MSPS, charge redistribution,
18-bit SAR ADC.
2. Superior Linearity.
The AD7643 has no missing 18-bit code.
3. Internal Reference.
The AD7643 has a 2.048 V internal reference with a typical
drift of ±8 ppm/°C and an on-chip TEMP sensor.
4. Single-Supply Operation.
The AD7643 operates from a 2.5 V single supply.
5. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with 2.5 V, 3.3 V, or
5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD7643 Datasheet, Funktion
AD7643
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
Symbol
SYNC to SCLK First Edge Delay Minimum
t18
Internal SCLK Period Minimum
t19
Internal SCLK Period Maximum
t19
Internal SCLK High Minimum
t20
Internal SCLK Low Minimum
t21
SDOUT Valid Setup Time Minimum
t22
SDOUT Valid Hold Time Minimum
t23
SCLK Last Edge to SYNC Delay Minimum
t24
BUSY High Width Maximum
t28
www.DataSheet4U.com
0011
0 1 0 1 Unit
1 3 3 3 ns
8 16 32 64 ns
20 40 70 135 ns
2 8 16 32 ns
2 8 16 32 ns
1 5 5 5 ns
0 0.5 10 30 ns
0 0.5 9 26 ns
0.84 1.14 1.72 2.88 μs
500µA
IOL
TO OUTPUT
PIN CL
50pF
1.4V
500µA
IOH
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 6 of 28

6 Page









AD7643 pdf, datenblatt
AD7643
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
65536
131072
CODE
196608
262144
Figure 5. Integral Nonlinearity vs. Code
40000
35000
33606
σ = 1.67
VREF = 2.5V
30000
25000
23521
26875
20000
15000
17320
13376
10000
5000
4848
3062
0 0 1 3 59 228
6371
1295 488 16 3 0
CODE IN HEX
Figure 6. Histogram of 131,072 Conversions of a DC Input at
the Code Center (External Reference)
2.0486
2.0484
2.0482
2.0480
2.0478
2.0476
2.0474
2.0472
2.0470
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
Figure 7. Typical Reference Voltage Output vs. Temperature (2 Units)
www.DataSheet4U.com
1.25
1.0
0.5
0
–0.5
–1.0
0
35000
30000
25000
65536
131072
196608
CODE
Figure 8. Differential Nonlinearity vs. Code
262144
28621
24350
σ = 2.04
VREF = 2.048V
20000
15000
18613
15505
10000
5000
4726 5401
0 21 28 305 665
16141
10173
3807
2306
297 108 3
2
CODE IN HEX
Figure 9. Histogram of 131,072 Conversions of a DC Input at
the Code Center (Internal Reference)
12
10
GAIN ERROR
8
6
4
2
0
ZERO ERROR
–2
–4
–6
–8
–10
–12
–55 –35 –15
5
25 45 65 85 105
TEMPERATURE (°C)
Figure 10. Zero Error, Gain Error vs. Temperature
125
Rev. 0 | Page 12 of 28

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