|
|
PDF 74LVC2G240 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G240 | |
| Descripción | Dual inverting buffer/line driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74LVC2G240 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
74LVC2G240
Dual inverting buffer/line driver; 3-state
Rev. 04 — 29 February 2008
www.DataSheet4U.com
Product data sheet
1. General description
The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state
outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at
pins nOE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger
action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G240 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing a damaging backflow current through the device when it is
powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page  
NXP Semiconductors
74LVC2G240
www.DataSheet4U.com
Dual inverting buffer/line driver; 3-state
9. Recommended operating conditions
Table 6.
Symbol
VCC
VI
VO
Operating conditions
Parameter
supply voltage
input voltage
output voltage
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
10. Static characteristics
Conditions
VCC = 1.65 V to 5.5 V;
Enable mode
VCC = 1.65 V to 5.5 V;
Disable mode
VCC = 0 V; Power-down mode
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
Min
1.65
0
0
0
0
−40
-
-
Max
5.5
5.5
VCC
5.5
5.5
+125
20
10
Unit
V
V
V
V
V
°C
ns/V
ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage
VCC = 1.65 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
2.0
0.7 × VCC
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
VCC = 2.7 V to 3.6 V
-
VCC = 4.5 V to 5.5 V
-
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
IO = 4 mA; VCC = 1.65 V
-
IO = 8 mA; VCC = 2.3 V
-
IO = 12 mA; VCC = 2.7 V
-
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
VCC − 0.1
IO = −4 mA; VCC = 1.65 V
1.2
IO = −8 mA; VCC = 2.3 V
1.9
IO = −12 mA; VCC = 2.7 V
2.2
IO = −24 mA; VCC = 3.0 V
2.3
IO = −32 mA; VCC = 4.5 V
3.8
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
Typ[1] Max
--
--
--
--
- 0.35 × VCC
- 0.7
- 0.8
- 0.3 × VCC
- 0.1
- 0.45
- 0.3
- 0.4
- 0.55
- 0.55
--
--
--
--
--
--
±0.1 ±5
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
74LVC2G240_4
Product data sheet
Rev. 04 — 29 February 2008
© NXP B.V. 2008. All rights reserved.
5 of 16
5 Page 
NXP Semiconductors
74LVC2G240
www.DataSheet4U.com
Dual inverting buffer/line driver; 3-state
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
y
Z
8
5
pin 1 index
E
c
HE
A A2
A1
1
e
4
bp w M
detail X
A
X
vM A
Q
(A3)
θ
Lp
L
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1) E(2)
e
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
HE
3.2
3.0
OUTLINE
VERSION
SOT765-1
IEC
REFERENCES
JEDEC
JEITA
MO-187
L Lp Q v w y Z(1) θ
0.4
0.40 0.21
0.15 0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
Fig 10. Package outline SOT765-1 (VSSOP8)
74LVC2G240_4
Product data sheet
Rev. 04 — 29 February 2008
© NXP B.V. 2008. All rights reserved.
11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 74LVC2G240.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74LVC2G240 | Dual inverting buffer/line driver | NXP Semiconductors |
| 74LVC2G241 | Dual buffer/line driver | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |