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AD10680 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD10680
Beschreibung 100 MSPS A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
AD10680 Datasheet, Funktion
Preliminary Technical Data
www.DataSheet4U.com
16-Bit, 100 MSPS A/D Converter
AD10680
FEATURES
100 MSPS sample rate
SNR of 85 dBFS @10 MHz
SFDR of 85 dBFS @10 MHz
VSWR of 1:1.5
AC-coupled input signal conditioning
Enhanced signal-to-noise ratio
Differential ENCODE signal
LVDS output levels
Twos complement output data
APPLICATIONS
Communications test equipment
Radar and satellite subsystems
Phased array antennas—digital beams
Multichannel, multimode receivers
Secure communications
Wireless and wired communications
GENERAL DESCRIPTION
The AD10680 is a 16-bit analog-to-digital converter (ADC)
with a transformer-coupled, analog input and digital
postprocessing for enhanced signal-to-noise ratio (SNR). The
product operates at a 100 MSPS conversion rate with
outstanding dynamic performance. Internal filters can be
digitally selected for the appropriate bandwidth or externally
programmed.
The AD10680 requires 5.0 V analog, 3.3 V analog, 3.3 V digital,
2.5 V digital, and a 1.2V digital supply, and a differential encode
signal. No external reference is required.
Performance is rated over a 0°C to 60°C case temperature range.
FUNCTIONAL BLOCK DIAGRAM
ENCODE
AD10680
ADC
A
2
OVER RANGE
AIN
DIGITAL
POST
PROCESSING
32
D0 TO D15
ADC
B
2 DATA CLOCK
OUTPUT
ENCODE
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate up to 100 MSPS.
2. Input signal conditioning with optimized dynamic
performance to 40 MHz.
3. Additional performance options are available, such as
increased SNR performance with digitally selectable input
bandwidths, digitally selectable full-scale input ranges, and
digitally selectable Nyquist zones. Contact sales for more
information.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD10680 Datasheet, Funktion
AD10680
THEORY OF OPERATION
The AD10680 uses two, high speed 16 bit ADCs with an
interleaved-averaging algorithm to improve the SNR. The
AD10680 is optimized for a 40 MHz bandwidth centered in the
first Nyquist zone. The AD10680 provides a single-ended,
analog input pin with a full-scale input range of 2.2 V p-p. The
analog input is designed for 50 Ω input impedance. The
AD10680’s differential ENCODE inputs are ac-coupled and
internally supplied to the two16 bit ADCs. The digital outputs
from the two ADCs are applied to the field-programmable gate
array (FPGA) for postprocessing. The result is a 16-bit parallel
LVDS word coded as twos complement.
INPUT STAGE
The user is provided with a single-to-differential, transformer-
coupled input. The input impedance is 50 Ω and requires a
2.2 V p-p input level to achieve full scale.
ENCODING THE AD10680
The AD10680’s differential ENCODE signal must be a high
quality, low phase noise source to prevent performance
degradation. The clock input must be treated as an analog input
signal because aperture jitter can affect dynamic performance.
For optimum performance, the AD10680 must be clocked
differentially.
ANALOG AND DIGITAL POWER SUPPLIES
Care must be taken when selecting a power source. Linear
supplies are recommended. Switching supplies tend to have
radiated components that can be coupled into the ADCs. The
AD10680 features separate analog and digital supply and
ground currents, helping to minimize digital corruption of
sensitive analog signals.
Preliminary Techwnwiwc.DaaltaDShaeteat4U.com
The 3.3 V digital supply provides power to the digital output
section of the ADCs. The 1.2 V and 2.5 V digital supplies
provide power for the FPGA. The digital supplies should be
decoupled to digital ground (DGND).
The 5.0 V and 3.3 V analog supplies provide power to the
analog sections of the ADCs. Decoupling capacitors are
strategically placed throughout the circuit to provide low
impedance noise shunts to ground. The analog supplies should
be decoupled to analog ground (AGND).
ANALOG AND DIGITAL GROUNDING
Although the AD10680 provides separate analog and digital
ground pins, the device should be treated as an analog
component. Proper grounding is essential in high speed, high
resolution systems. Multilayer printed circuit boards (PCBs) are
recommended to provide optimal grounding and power
distribution. The use of power and ground planes provides
distinct advantages. Power and ground planes minimize the
loop area encompassed by a signal and its return path,
minimize the impedance associated with power and ground
paths, and provide a distributed capacitor formed by the power
plane, printed circuit board material, and ground plane. The
AD10680 unit has five metal standoffs used to fasten the
AD10680 to the customer’s PCB. The AD10680 pin connections
mate to a connector (FSI-115-06-L-D-AD-TR for J2 and J3 and
FSI-110-06-L-D-AD-TR for J1).
Rev. PrA | Page 6 of 8

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