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PDF AD9974 Data sheet ( Hoja de datos )
| Número de pieza | AD9974 | |
| Descripción | CCD Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Dual-Channel, 14-Bit, CCD Signal
Processor with Precision Timing Core
AD9974
FEATURES
1.8 V analog and digital core supply voltage
Correlated double sampler (CDS) with
−3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 65 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 240 ps resolution @ 65 MHz
On-chip 3 V horizontal and RG drivers
100-lead, 9 mm × 9 mm, 0.8 mm pitch, CSP_BGA package
Internal low dropout (LDO) regulator circuitry
APPLICATIONS
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
GENERAL DESCRIPTION
The AD9974 is a highly integrated, dual-channel, charge-
coupled device (CCD) signal processor for high speed digital
video camera applications. Each channel is specified at pixel
rates of up to 65 MHz. The AD9974 consists of a complete
analog front end (AFE) with analog-to-digital conversion,
combined with a programmable timing driver. The Precision
Timing™ core allows adjustment of high speed clocks with
approximately 240 ps resolution at 65 MHz operation.
Each AFE includes black level clamping, CDS, VGA, and
a 65 MSPS, 14-bit ADC. The timing driver provides the high
speed CCD clock drivers for the RG_A, RG_B, H1_A to H4_A,
and H1_B to H4_B outputs. A 3-wire serial interface is used to
program each channel of the AD9974.
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,
the AD9974 is specified over an operating temperature range of
−25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT_A REFB_A
REFT_B REFB_B
CCDINP_A
CCDINM_A
CCDINP_B
CCDINM_B
AD9974
VREF_A
CDS
–3, 0, +3, +6dB
–3, 0, +3, +6dB
CDS
VREF_B
VGA
6dB TO 42dB
6dB TO 42dB
VGA
ADC
CLAMP
CLAMP
ADC
14
DOUT_A
14
DOUT_B
1.8V OUTPUT
LDO A
1.8V OUTPUT
LDO B
INTERNAL CLOCKS
RG_A
RG_B
H1_A TO H4_A
H1_B TO H4_B
4 HORIZONTAL
DRIVERS
4
PRECISION
TIMING
CORE
SYNC
GENERATOR
INTERNAL
REGISTERS
CLI_A
CLI_B
SCK_A
SCK_B
HD_A VD_A HD_B VD_B
Figure 1.
SL_A SDATA_A SL_B SDATA_B
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
AD9974
DIGITAL SPECIFICATIONS
X = A = B, IOVDD_X = 1.6 V to 3.6 V, RGVDD_X = HVDD_X = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
LOGIC INPUTS
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Capacitance (CIN)
LOGIC OUTPUTS
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
CLI INPUT (CLI_BIAS = 0)
High Level Input Voltage (VIHCLI)
Low Level Input Voltage (VILCLI)
H-DRIVER OUTPUTS
High Level Output Voltage at Maximum Current (VOH)
Low Level Output Voltage at Maximum Current
Maximum Output Current (Programmable) (VOL)
Maximum Load Capacitance
Min
Typ Max
Unit Test Conditions/Comments
IOVDD − 0.6
0.6
10
10
10
V
V
μA
μA
pF
IOVDD − 0.5
0.5
V IOH = 2 mA
V IOL = 2 mA
IOVDD/2 + 0.5
V
IOVDD/2 − 0.5 V
HVDD − 0.5
100
0.5
30
V
V
mA
pF
Rev. A | Page 5 of 52
5 Page 
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
TOTAL POWER
150
3.3V SUPPLIES
100
50
1.8V SUPPLIES
0
20 25 30 35 40 45 50 55 60 65
SAMPLE RATE (MHz)
Figure 4. Power vs. Sample Rate
180
160
140
120
100
80
60
40
20
0
0
5 10 15 20 25 30 35
VGA GAIN (dB)
Figure 5. RMS Output Noise vs. VGA Gain
40
45
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2k 4k 6k 8k 10k 12k 14k 16k
ADC OUTPUT CODE
Figure 6. Differential Nonlinearity
AD9974
10
8
6
4
2
0
–2
–4
–6
–8
0 2k 4k 6k 8k 10k 12k 14k 16k
ADC OUTPUT CODE
Figure 7. Integral Nonlinearity
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1k 3k 5k 7k 9k 11k 13k 15k
ADC OUTPUT CODE
Figure 8. Linearity Mismatch vs. ADC Output Code
Rev. A | Page 11 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9974.PDF ] | |
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