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Teilenummer | AD5390 |
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Beschreibung | 12-/14-Bit Voltage Output DACs | |
Hersteller | Analog Devices | |
Logo | ||
Gesamt 44 Seiten 8-/16-Channel, 3 V/5 V, Serial Input, Single-
Supply, 12-/14-Bit Voltage Output DACs
AD5390/AD5391/AD5392
FEATURES
INTEGRATED FUNCTIONS
AD5390: 16-channel, 14-bit voltage output DAC
Channel monitor
AD5391: 16-channel, 12-bit voltage output DAC
Simultaneous output update via LDAC
AD5392: 8-channel, 14-bit voltage output DAC
Guaranteed monotonic
INL: ±1 LSB max (AD5391)
±3 LSB max (AD5390-5/AD5392-5)
±4 LSB max (AD5390-3/AD5392-3)
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
www.DTaetmaSpheeraettu4Ure.croamnge: −40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package types:
64-lead LFCSP (9 mm × 9 mm)
52-lead LQFP (10 mm × 10 mm)
User interfaces:
Serial SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
(featuring data readback)
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Instrumentation and industrial control
Power amplifier control
Level setting (ATE)
Control systems
Microelectromechanical systems (MEMs)
Variable optical attenuators (VOAs)
Optical transceivers (MSA 300, XFP)
I2C®-compatible interface
FUNCTIONAL BLOCK DIAGRAM
DVDD (×2)
DGND (×2)
AVDD (×2)
AGND (×2) DAC_GND (×2) REF_GND REFOUT/REFIN SIGNAL_GND (×2)
AD5390
1.25V/2.5V
REFERENCE
SPI/I2C
DCEN/AD1
DIN/SDA
SCLK/SCL
SYNC/AD0
SDO
BUSY
PD
CLR
RESET
MON_IN1
MON_IN2
INTERFACE
CONTROL
LOGIC
STATE
MACHINE
AND
CONTROL
LOGIC
POWER-ON
RESET
VIN0 VIN15
MUX
14 INPUT 14
REG
0
14 m REG0
14 c REG0
14 INPUT 14
REG
1
14 m REG1
14 c REG1
14 DAC 14
REG
0
DAC 0
14 DAC 14
REG
1
DAC 1
14 INPUT 14
REG
6
14 m REG6
14 c REG6
14 INPUT 14
REG
7
14 m REG7
14 c REG7
14 DAC 14
REG
6
DAC 6
14 DAC 14
REG
7
DAC 7
×2
RR
RR
RR
RR
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 15
MON_OUT
Figure 1.
LDAC
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD5390/AD5391/AD5392
AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.
Table 3. AD5390-5/AD5391-5/AD5392-5 AC Characteristics1
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
AD5390/AD5392
AD5391
Slew rate2
www.DDaitgaitSahle-teot-4AUn.acloogmGlitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz)
Output Noise Spectral Density
@ 1 kHz
@ 10 kHz
All Unit
1
8 µs typ
10 µs max
6 µs typ
8 µs max
3 V/µs typ
2 V/µs typ
12 nV-s typ
15 mV typ
100 dB typ
1 nV-s typ
0.8 nV-s typ
0.1 nV-s typ
15 µV p-p typ
40 µV p-p typ
150 nV/(Hz)1/2 typ
100 nV/(Hz)1/2 typ
Test Conditions/Comments
¼ scale to ¾ scale change settling to ±1 LSB.
¼ scale to ¾ scale change settling to ±1 LSB.
Boost mode on.
Boost mode off.
See Terminology section.
See Terminology section.
Effect of input bus activity on DAC output under test.
External reference midscale loaded to DAC.
Internal reference midscale loaded to DAC.
1 Guaranteed by characterization, not production tested.
2 The slew rate can be adjusted via the current boost control bit in the DAC control register.
Rev. A | Page 6 of 44
6 Page AD5390/AD5391/AD5392
SCLK
SYNC
DIN
SDO
www.DataSheet4U.com
24
t7A
48
DB23
DB0
DB23'
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB23
DB0
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
TO
OUTPUT
PIN
200µA
IOL
CL
50pF
200µA
IOH
VOH (MIN) OR
VOL (MAX)
Figure 5. Load Circuit for Digital Output Timing
Rev. A | Page 12 of 44
12 Page | ||
Seiten | Gesamt 44 Seiten | |
PDF Download | [ AD5390 Schematic.PDF ] |
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