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R1EX25004ATA00I Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R1EX25004ATA00I
Beschreibung Serial Peripheral Interface Electrically Erasable and Programmable Read Only Memory
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 22 Seiten
R1EX25004ATA00I Datasheet, Funktion
R1EX25002ASA00I/R1EX25004ASA00I
R1EX25002ATA00I/R1EX25004ATA00I
Serial Peripheral Interface
2k EEPROM (256-word × 8-bit)
4k EEPROM (512-word × 8-bit)
Electrically Erasable and Programmable Read Only Memory
REJ03C0361-0001
Preliminary
Rev.0.01
Feb.21.2008
Description
www.DaRt1aEShXe2e5tx4xUx.cSomeries is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 16-byte
page programming function to make it’s write operation faster.
.
Features
Single supply: 1.8 V to 5.5 V
Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
Power dissipation:
Standby: 2µA (max)
Active (Read): 2 mA (max)
Active (Write): 2.5 mA (max)
Automatic page write: 16-byte/page
Write cycle time: 5 ms
Endurance: 106 Erase/Write Cycles
Data retention: 10 Years
Small size packages: SOP-8pin, TSSOP-8pin
Shipping tape and reel
TSSOP-8pin: 3,000 IC/reel
SOP-8pin : 2,500 IC/reel
Temperature range: 40 to +85 °C
Lead free product.
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications
REJ03C0361-0001 Rev.0.01 Feb.21.2008
page 1 of 20






R1EX25004ATA00I Datasheet, Funktion
R1EX25002Axx00I/R1EX25004Axx00I
(Ta = 40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol
Alt
Min
Max
Unit Notes
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
www.DaCtlaocShkeheigt4hUs.ceotump time before HOLD active
Clock high setup time before HOLD not
active
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
tCHHH
fSCK
tCSS1
tCSS2
tCS
tCSH
tCLH
tCLL
tRC
tFC
tDSU
tDH
100
100
150
100
100
150
150
30
50
140
90
120
120
3 MHz
ns
ns
ns
ns
ns
ns
ns
1 µs
1 µs
ns
ns
ns
ns
ns
ns
1
1
2
2
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output low-Z
HOLD low to output high-Z
Write time
Erase / Write Endurance
tSHQZ
tDIS
tCLQV
tV
tCLQX
tHO
0
tQLQH
tRO
tQHQL
tFO
tHHQX
tLZ
tHLQZ
tHZ
tW tWC
  106
200 ns
120 ns
ns
100 ns
100 ns
100 ns
100 ns
5 ms
cycles
2
2
2
2
2
3
Notes: 1. tCH + tCL 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
Value guaranteed by characterization, not 100% tested in products.
106cycles (Ta = 25°C)
105cycles (Ta = 85°C)
REJ03C0361-0001 Rev.0.01 Feb.25.2008
page 6 of 20

6 Page









R1EX25004ATA00I pdf, datenblatt
R1EX25002Axx00I/R1EX25004Axx00I
Read Status Register (RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at
any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is
recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also
possible to read the Status Register continuously, as shown in the following figure.
Read Status Register (RDSR) Sequence
VIH
S VIL
VIH
W VIL
C
www.DataSheet4U.com
VIH
VIL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VIH
D
VIL
Q
High-Z
Status Register Out
7 6 5 4 32 1 07
The status and control bits of the Status Register are as follows:
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the
internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write or Write Status
Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When
one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Status
Register Format table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can
be written provided that the Hardware Protected mode has not been set.
REJ03C0361-0001 Rev.0.01 Feb.25.2008
page 12 of 20

12 Page





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