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PCA9507 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCA9507
Beschreibung 2-wire serial bus extender
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 20 Seiten
PCA9507 Datasheet, Funktion
PCA9507
2-wire serial bus extender for HDMI DDC I2C-bus and SMBus
Rev. 01 — 7 February 2008
Product data sheet
1. General description
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The PCA9507 is a 2-wire serial bus extender providing 3.3 V to 5 V level shift that allows
up to 18 meters bus extension for reliable DDC, I2C-bus or SMBus applications. While
retaining all the operating modes and features of the I2C-bus system during the level
shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both
the data (SDA) and the clock (SCL) line as well as the rise time accelerator on port A
enabling the bus to drive a load up to 1400 pF or distance of 18 m on port A, and 400 pF
on port B. Using the PCA9507 enables the system designer to isolate bus capacitance to
meet HDMI DDC version 1.3 distance specification. The SDA and SCL pins are
overvoltage tolerant and are high-impedance when the PCA9507 is unpowered.
The port B drivers with static level offset behave much like the drivers on the PCA9515
device, while the port A drivers integrate the rise time accelerator, sink more current and
eliminate the static offset voltage. This results in a LOW on port B translating into a nearly
0 V LOW on port A. The static level offset design of the port B I/O drivers prevent them
from being connected to another device that has rise time accelerator including the
PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516A, PCA9517
(B-side), or PCA9518. The port A sides of two or more PCA9507s can be connected
together, however, to allow a star topography with port A on the common bus, and port A
can be connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9507s can be connected in series, port A to port B, with no build-up in offset voltage
with only time of flight delays to consider. Rise time accelerator on port A is turned on
when input threshold is above 0.3VCC(A).
The PCA9507 drivers are not enabled unless VCC(A) and VCC(B) are above 2.7 V. The EN
pin can also be used to turn the drivers on and off under system control. Caution should
be observed to only change the state of the enable pin when the bus is idle. The output
pull-down on the port B internal buffer LOW is set for approximately 0.5 V, while the input
threshold of the internal buffer is set about 70 mV lower (0.43 V). When the port B I/O is
driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a
lock-up condition from occurring.
2. Features
I 2 channel, bidirectional buffer isolates capacitance allowing 1400 pF on port A and
400 pF on port B
I Exceeds 18 meters (above the maximum distance for HDMI DDC)
I Rise time accelerator and normal I/O on port A
I Static level offset on port B
I Voltage level translation from 2.7 V to 5.5 V
I Upgrade replacement over PCA9517 for cable application






PCA9507 Datasheet, Funktion
NXP Semiconductors
PCA9507
2-wire serial bus extender for HDMI DDC I2C-bus and SMBus
6.3.2 Port B (SDAB and SCLB)
SDAB and SCLB are standard I2C-bus with static level offset that has no rise time
accelerator. The static level offset produces an output LOW of 0.5 V (typical) at 6 mA. As
with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH
levels. The size of these pull-up resistors depends on the system requirement, and should
meet the current sinking capability of the device that drives the buffer, as well as that of
the buffer. The minimum and maximum pull-up resistors are determined and the pull-up
resistor’s value is chosen to be within the minimum and maximum range.
Using Equation 1, calculate the minimum pull-up resistor value:
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RPU(min) = V-----C---C----(-B--I--)O-(--m-L---a(--mx---)a---x--)--0---.--4-----V---
(1)
Where:
RPU(min) is the minimum pull-up resistor value for the open-drain SCLB and SDAB.
VCC(B)(max) is the maximum supply rail of the pull-up resistor.
0.4 V is the maximum VOL of the device that drives the buffer on logic LOW.
IOL(max) at VOL = 0.4 V is the maximum sink current of the device that drives the buffer
on logic LOW.
The maximum pull-up resistor should also be sized such that the RC time constant meets
the standard I2C-bus rise time, which is 1 µs for Standard-mode (100 kHz) or 300 ns for
Fast-mode (400 kHz). DDC bus complies with the I2C-bus Standard-mode and operates
below 100 kHz, and maximum rise time is 1 µs using a simplified RC equation.
Using Equation 2, calculate the maximum pull-up resistor value:
RPU (max) × CL(max) = 1.2 × tr
(2)
Where:
RPU(max) is the maximum allowable pull-up resistor on the SCLB and SDAB in order to
meet the I2C-bus rise time specification.
CL(max) is the maximum allowable capacitance load (include the capacitance of driver,
the line, and the buffer) in order to meet the rise time specification.
tr is the rise time specified as 1 µs (for bus speed 100 kHz or lower) and 300 ns (for bus
speed 400 kHz or lower).
The chosen pull-up resistor RPU is: RPU(min) RPU RPU(max).
PCA9507_1
Product data sheet
Rev. 01 — 7 February 2008
© NXP B.V. 2008. All rights reserved.
6 of 20

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PCA9507 pdf, datenblatt
NXP Semiconductors
PCA9507
2-wire serial bus extender for HDMI DDC I2C-bus and SMBus
Table 5. Static characteristics …continued
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = 40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Enable
VIL
VIH
IIL(EN)
LOW-level input voltage
HIGH-level input voltage
LOW-level input current on pin
EN
VI = 0.2 V, EN; VCC = 3.6 V
0.5 -
0.7VCC(B) -
- 10
ILI input leakage current
Ci input capacitance
VI = VCC
VI = 3.0 V or 0 V
1 -
-6
Max Unit
+0.3VCC(B) V
5.5 V
30 µA
+1 µA
7 pF
[1] LOW-level supply voltage.
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[2] VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the
SDAB/SCLB lines.
[3] VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.
10. Dynamic characteristics
Table 6. Dynamic characteristics
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = 40 °C to +85 °C; unless otherwise specified.[1][2]
Symbol Parameter
Conditions
Min
tPLH LOW-to-HIGH propagation delay port B to port A; Figure 15
[4] 90
tPHL HIGH-to-LOW propagation delay port B to port A; Figure 13
55
tTLH LOW to HIGH output transition time port A; Figure 13
22
tTHL HIGH to LOW output transition time port A; Figure 13
tPLH LOW-to-HIGH propagation delay port A to port B; Figure 14
tPHL HIGH-to-LOW propagation delay port A to port B; Figure 14
20
[5] 140
[5] 130
tTLH LOW to HIGH output transition time port B; Figure 14
100
tTHL HIGH to LOW output transition time port B; Figure 14
20
tsu set-up time
EN HIGH before START condition [6] 100
th hold time
EN HIGH after STOP condition
[6] 100
Typ[3]
165
91
48
42
218
91
173
39
-
-
Max
350
180
80
100
310
330
260
100
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1] Times are specified with loads of 1.35 kpull-up resistance and 57 pF load capacitance on port B, and 450 pull-up resistance and
57 pF load capacitance on port A. Different load resistance and capacitance will alter the RC time constant, thereby changing the
propagation delay and transition times.
[2] Pull-up voltages are VCC(A) on port A and VCC(B) on port B.
[3] Typical values were measured with VCC(A) = 3.3 V at Tamb = 25 °C, unless otherwise noted.
[4] The tPLH delay data from port B to port A is measured at 0.5 V on port B to 0.3VCC(A) on port A.
[5] The proportional delay data from port A to port B is measured at 0.3VCC(A) on port A to 0.3VCC(B) on port B.
[6] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
PCA9507_1
Product data sheet
Rev. 01 — 7 February 2008
© NXP B.V. 2008. All rights reserved.
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