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PCA9502 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCA9502
Beschreibung 8-bit I/O expander
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 25 Seiten
PCA9502 Datasheet, Funktion
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
Rev. 03 — 13 October 2006
Product data sheet
1. General description
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The PCA9502 is an 8-bit I/O expander with I2C-bus/SPI host interface. The device comes
in a very small HVQFN24 package, which makes it ideally suitable for hand-held, battery
operated applications.
The device also supports software reset, which allows the host to reset the device at any
time, independent of the hardware reset signal.
2.1 General features
I Selectable I2C-bus or SPI interface
I 3.3 V or 2.5 V operation
I Industrial temperature range: 40 °C to +85 °C
I Eight programmable I/O pins
I Software reset
I Industrial and commercial temperature ranges
I Available in HVQFN24 package
I 16 hardware-selectable slave addresses
2.2 I2C-bus features
I Noise filter on SCL/SDA inputs
I 400 kbit/s (maximum)
I Compliant with I2C-bus Fast-mode
I Slave mode only
2.3 SPI features
I 15 Mbit/s maximum speed
I Slave mode only
I SPI Mode 0
3. Applications
I Factory automation and process control
I Portable and battery operated devices
I Cellular data devices






PCA9502 Datasheet, Funktion
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
8.2 Programmable I/O pins State register (IOState)
When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each
register bit will be transferred to the corresponding IO pin programmed as output.
Table 8.
Bit
7:0
IOState register (address 0x0B) bit description
Symbol
Description
IOState
Write this register: set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register: return states of all pins
www.DataSheet4U.com8.3 I/O Interrupt Enable register (IOIntEna)
This register enables the interrupt due to a change in the I/O configured as inputs.
Table 9.
Bit
7:0
IOIntEna register (address 0x0C) bit description
Symbol
Description
IOIntEna
input interrupt enable
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt
8.4 I/O Control register (IOControl)
Table 10. IOControl register (address 0x0E) bit description
Bit Symbol Description
7:4 -
reserved for future use
3
SReset
software reset
A write to this bit will reset the device. Once the device is reset this
bit is automatically set to 0.
2:1 -
reserved for future use
0
IOLatch
enable/disable inputs latching
0 = input values are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.
Example: If GPIO4 input was as logic 0 and the input goes to logic 1
then back to logic 0, the IOState register will capture this change and
an interrupt is generated (if enabled). When the read is performed on
the IOState register, the interrupt is de-asserted, assuming there were
no additional input(s) that changed, and bit 4 of the IOState register
will read ‘1’. The next read of the IOState register should now read ‘0’.
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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PCA9502 pdf, datenblatt
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
S SLAVE ADDRESS W
A REGISTER ADDRESS A
nDATA
AP
White block: host to PCA9502
Grey block: PCA9502 to host
Fig 10. Master writes to slave
002aab047
www.DataSheet4U.com
The register read cycle (see Figure 11) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following sub-address.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal sub-address will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
S SLAVE ADDRESS W
A REGISTER ADDRESS A
S SLAVE ADDRESS R
A
nDATA
A LAST DATA
White block: host to PCA9502
Grey block: PCA9502 to host
Fig 11. Master read from Slave
Table 12.
Bit
7
6:3
2:1
0
Register address byte (I2C-bus)
Name
Function
- not used
A[3:0]
internal register select
- not used, set to 0
- not used
NA P
002aab048
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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