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PA7572 Schematic ( PDF Datasheet ) - Anachip

Teilenummer PA7572
Beschreibung Programmable Electrically Erasable Logic Array
Hersteller Anachip
Logo Anachip Logo 




Gesamt 10 Seiten
PA7572 Datasheet, Funktion
PA7572 PEEL Array™
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 24 I/Os, 14 inputs, 60 registers/latches
- Up to 72 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and -40
to +85 °C temperatures
wwIdwe.aDlaftoaSrhCeoetm4Ub.cinoamtorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
CMOS Electrically Erasable Technology
- Reprogrammable in 40-pin DIP, 44-pin PLCC and
TQFP packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
General Description
The PA7572 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on Anachip’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7572 offers a
versatile logic array architecture with 24 I/O pins, 14 input
pins and 60 registers/latches (24 buried logic cells, 12 input
registers/latches, 24 buried I/O registers/latches). Its logic
array implements 100 sum-of-products logic functions
divided into two groups each serving 12 logic cells. Each
group shares half (60) of the 120 product-terms available.
The PA7572’s logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7572 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. The
PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)
and 66.6MHz (fMAX) at moderate power consumption
140mA (100mA typical). Packaging includes 40-pin DIP
and 44-pin PLCC (see Figure 1). Anachip and popular
third-party development tool manufacturers provide
development and programming support for the PA7572.
Figure 1. Pin Configuration
Figure 2. Block Diagram
DIP (600 mil)
I/C L K 1
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/C L K 2
TQFP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
PLCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 4039 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 151617 18 19 20 21 22
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
08-15-001A
I/C L K
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
GND
2 Input/
G lobal Clock Pins
12 Input Pins
Input
Cells
( IN C )
Global Cells
Input Cells
I/O Cells
Logic Control Cells
PA7572
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/CLK 2
Global
Cells
124 (62X2)
Array Inputs
true and
2 complement
12 24
I/O
Cells
(IO C)
24 I/O Pins
Lo gic
A rra y
24 Buried
logic
Logic
A
B
Control
C Cells
D (LCC)
24
Logic
func tions
to I/O cells
4 sum terms
5 product terms
for Global Cells
96 sum terms
(four per LCC)
24
24 Logic Control Cells
up to 3 output functions per cell
(72 total output functions
possible)
08-15-002A
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10






PA7572 Datasheet, Funktion
This device has been designed and tested for the specified
operating ranges. Improper operation outside of these levels
is not guaranteed. Exposure to absolute maximum
ratings may cause permanent damage.
Table 1. Absolute Maximum Ratings
Symbol
Parameter
VCC Supply Voltage
VI, VO
Voltage Applied to Any Pin
IO Output Current
TST Storage Temperature
www.DataSThLeT et4U.com
Lead Temperature
Table 2. Operating Ranges
Symbol
Parameter
VCC Supply Voltage
TA Ambient Temperature
TR Clock Rise Time
TF Clock Fall Time
TRVCC
VCC Rise Time
Table 3. D.C. Electrical Characteristics
Conditions
Relative to Ground
Relative to Ground1
Per pin (IOL, IOH)
Soldering 10 seconds
Ratings
-0.5 to + 7.0
-0.5 to VCC + 0.6
±25
-65 to + 150
+300
Conditions
Commercial
Industrial
Commercial
Industrial
See Note 2
See Note 2
See Note 2
Min
4.75
4.5
0
-40
Over the Operating Range
Max
5.25
5.5
+70
+85
20
20
250
Symbol
Parameter
Conditions
Min Max
VOH
VOHC
VOL
VOLC
VIH
Output HIGH Voltage - TTL
Output HIGH Voltage -
CMOS
Output LOW Voltage - TTL
Output LOW Voltage -
CMOS
Input HIGH Level
VCC = Min, IOH = -4.0mA
VCC = Min, IOH = -10µA
VCC = Min, IOL = 16mA
VCC = Min, IOL = -10µA
2.4
VCC - 0.3
2.0
0.5
0.15
VCC + 0.3
VIL Input LOW Level
-0.3 0.8
IIL
Input Leakage Current
VCC = Max, GND VIN VCC
±10
IOZ
ISC
ICC11
Output Leakage Current
Output Short Circuit
Current4
VCC Current
I/O = High-Z, GND VO VCC
VCC = 5V, VO = 0.5V, TA= 25°C
VIN = 0V or VCC3,11
f = 25MHz
All outputs disabled4
±10
-30 -120
-20 75
50 (typ.)18
I-20 85
CIN7
COUT7
Input Capacitance5
Output Capacitance5
TA = 25°C, VCC = 5.0V @ f = 1 MHz
6
12
Unit
V
V
mA
°C
°C
Unit
V
°C
ns
ns
ms
Unit
V
V
V
V
V
V
µA
µA
mA
mA
pF
pF
Anachip Corp.
www.anachip.com.tw
6/10
Rev. 1.0 Dec 16, 2004

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