Datenblatt-pdf.com


GS8342D09E-333 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8342D09E-333
Beschreibung 36Mb SigmaQuad-II Burst
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8342D09E-333 Datasheet, Funktion
Preliminary
GS8342D08/09/18/36Ew-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/167
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaQuad-II
Burst of 4 SRAM
167 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb
and 144Mb devices
SigmaQuadFamily Overview
The GS8342D08/09/18/36E are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342D08/18/36E SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342D08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B4 RAMs always transfer
data in four packets, A0 and A1 are internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfers. Because the LSBs are tied off internally,
the address field of a SigmaQuad-II B4 RAM is always two
address pins less than the advertised index depth (e.g., the 2M
x 18 has a 512K addressable index).
Parameter Synopsis
tKHKH
tKHQV
- 333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.50 ns
Rev: 1.02 8/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology






GS8342D09E-333 Datasheet, Funktion
Preliminary
GS8342D08/09/18/36E-333/300/250/200/167
www.DataSheet4U.com
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW3
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
NW0–NW1
Nybble Write Control Pin
K Input Clock
K Input Clock
C Output Clock
C Output Clock
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock Input
TDO Test Data Output
VREF HSTL Input Reference Voltage
ZQ Output Impedance Matching Input
Qn Synchronous Data Outputs
Dn Synchronous Data Inputs
Doff Disable DLL when low
CQ Output Echo Clock
CQ Output Echo Clock
VDD Power Supply
VDDQ
Isolated Output Buffer Supply
VSS Power Supply: Ground
Note:
NC = Not Connected to die or any other pin
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Supply
Supply
Supply
Comments
Active High
Active Low
Active Low
x9/x18/x36 only
Active Low
x8 only
Active High
Active Low
Active High
Active Low
Active Low
1.8 V Nominal
1.5 or 1.8 V Nominal
Rev: 1.02 8/2005
6/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

6 Page









GS8342D09E-333 pdf, datenblatt
Preliminary
GS8342D08/09/18/36E-333/300/250/200/167
www.DataSheet4U.com
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150and 300. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
Separate I/O SigmaQuad-II B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
D
D
D
Q
Q
Q
Q
K
(tn-1)
Deselect
KKK
↑↑↑
(tn) (tn) (tn)
X11
K
(tn)
Deselect
K
(tn+1)
K
(tn+1½)
K
(tn+2)
K
(tn+2½)
K
(tn+1)
K
(tn+1½)
K
(tn+2)
K
(tn+2½)
X X — — Hi-Z Hi-Z — —
Write
X1X
Deselect
D2 D3 —
— Hi-Z Hi-Z —
Read
XX1
Deselect
X
X — — Q2 Q3 — —
Deselect
V10
Write
D0 D1 D2 D3 Hi-Z Hi-Z —
Deselect
V0X
Read
X X — — Q0 Q1 Q2 Q3
Read
VX0
Write
D0 D1 D2 D3 Q2 Q3 — —
Write V 0 X
Read
D2 D3 — — Q0 Q1 Q2 Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. Users should not clock in metastable addresses.
Rev: 1.02 8/2005
12/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

12 Page





SeitenGesamt 30 Seiten
PDF Download[ GS8342D09E-333 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GS8342D09E-33336Mb SigmaQuad-II BurstGSI Technology
GSI Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche