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PDF W3HG2128M72ACER-AD6 Data sheet ( Hoja de datos )

Número de pieza W3HG2128M72ACER-AD6
Descripción 2GB - 2x128Mx72 DDR2 SDRAM REGISTERED
Fabricantes White Electronic Designs　
Logotipo White Electronic Designs Logotipo



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No Preview Available ! W3HG2128M72ACER-AD6 Hoja de datos, Descripción, Manual

White Electronic Designs W3HG2128M72ACER-AD6
www.DataSheePt4RUE.cLoIMmINARY*
2GB – 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
FEATURES
240-pin, dual in-line very low profile (VLP) memory
module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM
components
VCC = VCCQ = 1.8V
VCCSPD = +1.7V to +3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# additive latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
ECC error detection and correction
Dual Rank
RoHS compliant
Package option
• 240 Pin VLP: 18.29mm (0.720") TYP
DESCRIPTION
The W3HG2128M72ACER is a 2x128Mx72 Double Data
Rate DDR2 SDRAM high density module based on DDR2
SDRAM components. This memory module consists
of eighteen stacks of 256Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4300
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
May 2006
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3HG2128M72ACER-AD6 pdf
White Electronic Designs W3HG2128M72ACER-AD6
www.DataSheetP4UR.EcoLmIMINARY
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
Operating one bank active-precharge current;
ICC0 tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
ICC1
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD =
tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as ICC4W
Precharge power-down current;
ICC2P All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge quiet standby current;
ICC2Q All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
Precharge standby current;
ICC2N All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
ICC3P All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
806
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ICC3N
ICC4W
ICC4R
ICC5B
ICC6
ICC7
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the
following page for detailed timing conditions
TBD
TBD
TBD
TBD
TBD
TBD
NOTE: ICC specs are based on MICRON components. Other DRAM manufacturers parameters may be different.
665 534 403 Units
1,720 1,530 1,530 mA
1,980 1,800 1,710 mA
180 180 180 mA
1,800 1,440 1,260 mA
1,980 1,620 1,440 mA
1,260 1,080 900
360 360 360
mA
mA
2,340 1,980 1,620 mA
2,880 2,430 2,070 mA
3,240 2,700 2,160 mA
7,560 7,200 6,840 mA
180 180 180 mA
5,130 4,770 4,230 mA
May 2006
Rev. 5
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3HG2128M72ACER-AD6 arduino
White Electronic Designs W3HG2128M72ACER-AD6
www.DataSheetP4UR.EcoLmIMINARY
ORDERING INFORMATION FOR AD6
Part Number
Speed/Data Rate
CAS Latency tRCD tRP
W3HG2128M72ACER806AD6xG**
400MHz/800Mb/s
6 66
W3HG2128M72ACER665AD6xG**
333MHz/667Mb/s
5 55
W3HG2128M72ACER534AD6xG
266MHz/533Mb/s
4 44
W3HG2128M72ACER403AD6xG
200MHz/400Mb/s
3 33
** Contact factory for availability
NOTES:
• RoHS compliant product. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
Height*
18.29mm (0.72") TYP
18.29mm (0.72") TYP
18.29mm (0.72") TYP
18.29mm (0.72") TYP
3.00
(0.118)
4.00
(0.157)
PACKAGE DIMENSIONS FOR AD6
Front View
133.35 (5.25)
5.00
(0.196)
4.00 (0.157)
1.50 ± 0.10
(0.059 ± 0.004)
18.29
(0.720) TYP
0.80 ± 0.05
(0.031 ± 0.002)
1.00 (0.039)
2.50 ± 0.20
(0.098 ± 0.007)
4.06
(0.160)
63.00 (2.48)
Back View
55.00 (2.165)
1.27
(0.050± -0.004)
May 2006
Rev. 5
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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