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GS8662Q09E-300 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8662Q09E-300
Beschreibung 72Mb SigmaQuad-II Burst
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8662Q09E-300 Datasheet, Funktion
165-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
GS8662Q08/09/18w/3w6wE.D-3at0a0Sh/2ee5t04U/2.c0o0m/167
72Mb SigmaQuad-II
Burst of 2 SRAM
300 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, and 36Mb and
future 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GSQ8662Q08/09/18/36E are built in compliance with
the SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B2 RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read or
write transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a SigmaQuad-II B2 RAM is always one address pin
less than the advertised index depth (e.g., the 4M x 18 has a
2048K addressable index).
Parameter Synopsis
tKHKH
tKHQV
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.01 9/2005
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology






GS8662Q09E-300 Datasheet, Funktion
Pin Description Table
Symbol
SA
NC
R
W
BW
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Write
BW0–BW3
Synchronous Byte Writes
NW0–NW1
Nybble Write Control Pin
K Input Clock
K Input Clock
C Output Clock
C Output Clock
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock Input
TDO Test Data Output
VREF HSTL Input Reference Voltage
ZQ Output Impedance Matching Input
Qn Synchronous Data Outputs
Dn Synchronous Data Inputs
Doff Disable DLL when low
CQ Output Echo Clock
CQ Output Echo Clock
VDD Power Supply
VDDQ
Isolated Output Buffer Supply
VSS Power Supply: Ground
Note:
NC = Not Connected to die or any other pin
Preliminary
GS8662Q08/09/18/36E-300/250/200/167
www.DataSheet4U.com
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Supply
Supply
Supply
Comments
Active Low
Active Low
Active Low
x9 only
Active Low
x18/x36 only
Active Low
x8 only
Active High
Active Low
Active High
Active Low
Active Low
1.8 V Nominal
1.5 or 1.8 V Nominal
Rev: 1.01 9/2005
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology

6 Page









GS8662Q09E-300 pdf, datenblatt
Preliminary
GS8662Q08/09/18/36E-300/250/200/167
www.DataSheet4U.com
Rev: 1.01 9/2005
12/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology

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