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GS8662S08E-250 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8662S08E-250
Beschreibung DDR SigmaSIO-II SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8662S08E-250 Datasheet, Funktion
Preliminary
GS8662S08/09/18/36E-333/300/250/200/167
www.DataSheet4U.com
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb Burst of 2
DDR SigmaSIO-II SRAM
333 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with future 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaRAMFamily Overview
GS8662S08/09/18/36 are built in compliance with the
SigmaSIO-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 4M x 18 has a 1M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
- 333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.01 9/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology






GS8662S08E-250 Datasheet, Funktion
Preliminary
GS8662S08/09/18/36Ew-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/167
Pin Description Table
Symbol
Description
Type Comments
SA Synchronous Address Inputs Input —
NC
No Connect
——
R/W
Read/Write Contol Pin
Input Write Active Low; Read Active High
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
x08 Version
BW0–BW1
Synchronous Byte Writes
Input
Active Low
x18 Version
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x36 Version
K
Input Clock
Input Active High
C
Output Clock
Input Active High
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input
ZQ
Output Impedance Matching Input
Input
K
Input Clock
Input Active Low
C
Output Clock
Output
Active Low
DOFF
DLL Disable
— Active Low
LD
Synchronous Load Pin
— Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
Dn
Synchronous Data Inputs
Input
Qn
Synchronous Data Outputs
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
Notes:
1. C, C, K, or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. NC = Not Connected to die or any other pin
Rev: 1.01 9/2005
6/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology

6 Page









GS8662S08E-250 pdf, datenblatt
Preliminary
GS8662S08/09/18/36Ew-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a
vendor-specified tolerance is between 150and 300. Periodic readjustment of the output driver impedance is necessary as the
impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts
in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets
and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum
level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for “0s” occur
whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A LD R/W
Current
Operation
DDQQ
KKK
(tn) (tn) (tn)
K
(tn)
K
(tn+1)
K
(tn+1)
K
(tn+1)
K
(tn+1)
X1X
Deselect
X — Hi-Z —
V01
Read
X — Q0 Q1
V00
Write
D0 D1 Hi-Z —
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. CQ is never tristated.
7. Users should not clock in metastable addresses.
Rev: 1.01 9/2005
12/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology

12 Page





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