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PDF AD8383 Data sheet ( Hoja de datos )
| Número de pieza | AD8383 | |
| Descripción | 6-Channel Output Decimating LCD | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8383 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Low Cost 10-Bit, 6-Channel Output
www.DataSheet4U.com
Decimating LCD DecDriver®
AD8383
FEATURES
High voltage drive to within 1.3 V of supply rails
Output short-circuit protection
High update rates
Fast, 100 Ms/s, 10-bit input data update rate
Low static power dissipation: 0.7 W
Includes STBY function
Voltage-controlled video reference (brightness) and
full-scale (contrast) output levels
INV bit reverses polarity of video signal
3.3 V logic, 9 V to 18 V analog supplies
High accuracy voltage outputs
Laser trimming eliminates the need for adjustments
Flexible logic
STSQ/XFR allow parallel AD8383 operation at various
resolutions
Fast settling into capacitive loads
30 ns settling time to 0.25% into 150 pF load
Slew rate 460 V/µs
Available in 48-lead 7 mm × 7 mm LFCSP package
APPLICATIONS
LCD analog column driver
PRODUCT DESCRIPTION
The AD8383 provides a fast, 10-bit latched decimating digital
input that drives six high voltage outputs. 10-bit input words are
sequentially loaded into six separate, high speed, bipolar DACs.
Flexible digital input format allows several AD8383s to be used
in parallel for higher resolution displays. STSQ synchronizes
sequential input loading, XFR controls synchronous output
updating, and R/L controls the direction of loading as either
left-to-right or right-to-left. Six channels of high voltage output
drivers drive to within 1.3 V of the rail. For maximum flexibility,
the output signal can be adjusted for dc reference, signal
inversion.
FUNCTIONAL BLOCK DIAGRAM
DB(0:9)
10
10 10 2-STAGE 10 DAC
LATCH
AD8383
10 2-STAGE 10 DAC
LATCH
STBY
BYP
BIAS
10 2-STAGE 10 DAC
LATCH
10 2-STAGE 10 DAC
LATCH
R/L
E/O
CLK
STSQ
XFR
10 2-STAGE 10 DAC
LATCH
SEQUENCE
CONTROL
10 2-STAGE 10 DAC
LATCH
SCALING
CONTROL
VREFHI VREFLO
INV V1 V2
Figure 1
VID0
VID1
VID2
VID3
VID4
VID5
The AD8383 is fabricated on the 26 V, fast bipolar XFHV
process developed by Analog Devices, Inc. This process
provides fast input logic, bipolar DACs with trimmed accuracy
and fast settling, high voltage, precision drive amplifiers on the
same chip.
The AD8383 dissipates 0.7 W nominal static power. The STBY
pin reduces power to a minimum with fast recovery.
The AD8383 is offered in a 48-lead, 7 mm × 7 mm × 0.85 mm
LFCSP package and operates over the commercial temperature
range of 0°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD8383www.DataSheet4U.com
ABSOLUTE MAXIMUM RATINGS
Table 2. AD8383 Stress Ratings
Parameter
Rating
Supply Voltages
AVCCx – AGNDx
18 V
DVCC – DGND
4.5 V
Input Voltages
Maximum Digital Input Voltages
DVCC + 0.5 V
Minimum Digital Input Voltages
Maximum Analog Input Voltages
Minimum Analog Input Voltages
Internal Power Dissipation8
LFCSP Package @ 25°C Ambient
DGND – 0.5 V
AVCC + 0.5 V
AGND – 0.5 V
3.8 W
Operating Temperature Range
0°C to 85°C
Storage Temperature Range
–65°C to +125°C
Lead Temperature Range (Soldering 10 sec) 300°C
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the
absolute maximum ratings for extended periods may reduce
device reliability.
8 48-Lead LFCSP Package:
θJA = 26°C/W (Still Air): JEDEC STD, 4-layer board with 0 CFM airflow
θJC = 20°C/W
ψJB = 11.0°C/W in Still Air
MAXIMUM POWER DISSIPATION
Junction Temperature
The maximum power that can be safely dissipated by the
AD8383 is limited by its junction temperature. The maximum
safe junction temperature for plastic encapsulated devices as
determined by the glass transition temperature of the plastic is
approximately 150°C. Exceeding this limit temporarily may
cause a shift in the parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can
result in device failure.
Overload Protection
The AD8383 employs a 2-stage overload protection circuit that
consists of an output current limiter and a thermal shutdown.
The maximum current at any one output of the AD8383 is
internally limited to 100 mA, average. In the event of a momen-
tary short-circuit between a video output and a power supply
rail (AVCC or AGND), the output current limit is sufficiently
low to provide temporary protection.
The thermal shutdown debiases the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short-circuit between a video output and a
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typical with a period
determined by the thermal time constant and the hysteresis of
the thermal trip point. The thermal shutdown provides long-
term protection by limiting the average junction temperature to
a safe level.
Operating Temperature Range
Production testing guarantees a minimum thermal shutdown
junction temperature (TJ) of at least 125°C.
To ensure operation at TJ < 125°C, it is necessary to limit the
maximum power dissipation as described in the Applications
section.
Exposed Paddle
The die paddle must be soldered to AVCC for reliable electrical
operation.
See the Applications section for details regarding use of the
exposed paddles to dissipate excess heat.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
5 Page 
THERMAL VIA STRUCTURE DESIGN
Effective heat transfer from the top to the inner and bottom
layers of the PCB requires thermal vias incorporated into the
thermal pad design. Thermal performance increases logarithmi-
cally with the number of vias, as shown in Figure 12. With the
AD8383 on a standard JEDEC PCB, θJA reaches its specified
value when a total of 16 vias are used. At a via count above 36,
θJA approaches its optimum value as the slope of the curve
approaches zero.
32
30
28
26
24
22
0
10 20 30
NUMBER OF VIAS
40
Figure 12. Thermal Performance vs. Number of Vias (on a JEDEC PCB)
Near optimum thermal performance of production PCBs is
attained when the number of vias is at least 36.
SOLDER MASKING
To minimize the formation of solder voids due to solder flowing
into the via holes (solder wicking), the via diameter should be
small. Solder masking of the via holes on the top layer of the
PCB plugs the via holes, inhibiting solder flow into the holes. To
optimize the thermal pad coverage, the solder mask diameter
should be no more than 0.1 mm larger than the via diameter.
AD8383www.DataSheet4U.com
REFERENCE PCB DESIGN
The top copper layer is shown in Figure 13.
7 mm
Figure 13. Recommended PCB Landing
The bottom thermal pad forms AVCC plane.
Thermal Pads
Top PCB Layer:
Bottom PCB Layer:
5.25 mm × 5.25 mm
5.25 mm × 5.25 mm
Thermal via structure
Diameter:
0.25 mm
Number of vias:
41
Via Grid Pitch:
0.5 mm
Miscellaneous
Perimeter Pads:
Solder Mask Swell:
0.5 mm × 0.25 mm
0.02 mm
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD8383.PDF ] | |
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